Patents by Inventor Michael Jarboe
Michael Jarboe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8035407Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: GrantFiled: April 4, 2011Date of Patent: October 11, 2011Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20110176374Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: ApplicationFiled: April 4, 2011Publication date: July 21, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Michael Jarboe, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Patent number: 7940066Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: GrantFiled: October 13, 2010Date of Patent: May 10, 2011Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20110026343Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Michael Jarboe, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Patent number: 7834615Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal.Type: GrantFiled: July 2, 2007Date of Patent: November 16, 2010Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20090013228Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Inventors: JAMES MICHAEL JARBOE, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20090009206Abstract: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively.Type: ApplicationFiled: July 2, 2007Publication date: January 8, 2009Inventors: James Michael Jarboe, JR., Sukanta Kishore Panigrahi, Vinay Agrawal, Neeraj P. Nayak
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Publication number: 20070107290Abstract: A locking system for firearms including a locking ring rotatably mounted to a bolt. As the bolt is moved through a bolt slide, the locking ring engages a cam member, which causes the locking ring to rotate about the bolt, which can remain fixed against rotation.Type: ApplicationFiled: July 31, 2006Publication date: May 17, 2007Inventors: Michael Keeney, Michael Jarboe
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Patent number: 7155637Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.Type: GrantFiled: April 29, 2003Date of Patent: December 26, 2006Assignee: Texas Instruments IncorporatedInventors: James Michael Jarboe, Jr., Nathan Weyer Wright, Nicholas Henry Schutt, Van Ho
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Publication number: 20050257681Abstract: An action rate control system for a gas operated firearm that includes an action sleeve and an action rate control cylinder. The action sleeve moves in a rearward direction in response to a volume of combustion gases that are generated during firing of the firearm and diverted from the barrel of the firearm through gas ports. The action rate control cylinder is connected to the action sleeve by a linkage that controls movement and slowing of the action sleeve as it approaches a rear limit for its movement. The resistance force generated by the rate control cylinder is a function of the velocity of the action sleeve during its movement. In another aspect, a gas operated firearm includes a barrel, a bolt assembly, an action system coupled to the bolt assembly, and a rate control cylinder coupled to the action system. The action system includes a sleeve assembly that is driven by a volume of combustion gases that are diverted from the barrel when a round of ammunition is fired.Type: ApplicationFiled: October 26, 2004Publication date: November 24, 2005Inventors: Michael Keeney, Michael Jarboe
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Publication number: 20050066564Abstract: A locking system for firearms including a locking ring rotatably mounted to a bolt. As the bolt is moved through a bolt slide, the locking ring engages a cam member, which causes the locking ring to rotate about the bolt, which can remain fixed against rotation.Type: ApplicationFiled: May 21, 2004Publication date: March 31, 2005Inventors: Michael Keeney, Michael Jarboe
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Publication number: 20040153793Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.Type: ApplicationFiled: April 29, 2003Publication date: August 5, 2004Applicant: Texas Instruments IncorporatedInventors: James Michael Jarboe, Nathan Weyer Wright, Nicholas Henry Schutt, Van Ho