Patents by Inventor Michael Jarchi

Michael Jarchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6810499
    Abstract: A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: October 26, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Satish Sridharan, Michael Jarchi, Timothy Coe
  • Patent number: 6738942
    Abstract: A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: May 18, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Satish Sridharan, Michael Jarchi
  • Patent number: 6694476
    Abstract: A semi-parallel forward error correction system. In one embodiment the forward error correction system includes a semi-parallel Reed-Solomon encoder and a semi-parallel Reed-Solomon decoder. Information symbols comprised of bytes are provided eight bytes in parallel to an encoder which in parallel forms eight bytes of a nonsystematic code word. On decoding, a code word is provided to a time multiplexed syndrome generator and key equation solver. An error locator polynomial from the key equation solver and the syndromes from the syndrome generator are provided to an error location and error magnitude unit, which includes a plurality of polynomial evaluator units which process an error locator polynomial in parallel.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: February 17, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Satish Sridharan, Michael Jarchi
  • Publication number: 20020049947
    Abstract: A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.
    Type: Application
    Filed: June 4, 2001
    Publication date: April 25, 2002
    Inventors: Satish Sridharan, Michael Jarchi, Timothy Coe