Patents by Inventor Michael Jassowski

Michael Jassowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11352133
    Abstract: The disclosure generally provides methods, systems and apparatus for networked drone systems. In an exemplary networked drone system, a plurality of smaller drones are attached to a fixed platform to increase delivery payload, distance, reliability and safety. As a drone nears charge depletion, it is replaced in-flight with a new drone. Thus, the networked drone system need not be grounded to replace the depleted drone. In another embodiment, flight efficiency is increased by providing collapsible wins to the networked drone system.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 7, 2022
    Assignee: INTEL CORPORATION
    Inventors: Michael Jassowski, Ashwin Thirunahari, Anil Nanduri, Baptiste Tripard
  • Patent number: 10324462
    Abstract: Systems and methods may use a drone swarm to increase cargo capacity. A drone swarm may include a networked drone system or two or more drones, such as a parent drone and a child drone. A method may include receiving support component balance information captured by an inertial measurement unit on the support component supported by a parent drone, adjusting movement of the parent drone according to a control system using the support component balance information, receiving an indication of a low battery in a drone in the networked drone system, the indication including an identification of a replacement drone to replace the drone with the low battery in the networked drone system, and sending a reconfiguration command to at least one child drone to incorporate the replacement drone in the networked drone system.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Michael A Jassowski, Ashwin S Thirunahari
  • Publication number: 20190047698
    Abstract: The disclosure generally provides methods, systems and apparatus for networked drone systems. In an exemplary networked drone system, a plurality of smaller drones are attached to a fixed platform to increase delivery payload, distance, reliability and safety. As a drone nears charge depletion, it is replaced in-flight with a new drone. Thus, the networked drone system need not be grounded to replace the depleted drone. In another embodiment, flight efficiency is increased by providing collapsible wins to the networked drone system.
    Type: Application
    Filed: December 28, 2017
    Publication date: February 14, 2019
    Applicant: Intel Corporation
    Inventors: Michael Jassowski, Ashwin Thirunahari, Anil Nanduri, Baptiste Tripard
  • Publication number: 20180188724
    Abstract: Systems and methods may use a drone swarm to increase cargo capacity. A drone swarm may include a networked drone system or two or more drones, such as a parent drone and a child drone. A method may include receiving support component balance information captured by an inertial measurement unit on the support component supported by a parent drone, adjusting movement of the parent drone according to a control system using the support component balance information, receiving an indication of a low battery in a drone in the networked drone system, the indication including an identification of a replacement drone to replace the drone with the low battery in the networked drone system, and sending a reconfiguration command to at least one child drone to incorporate the replacement drone in the networked drone system.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Michael Jassowski, Ashwin S. Thirunahari
  • Publication number: 20050269718
    Abstract: One embodiment of a method and system is disclosed. The method configures a plurality of bond pads on a die arranged in a staggered array. The staggered array includes an inner and outer ring of bond pads. A first plurality of driver cells are placed to the outside of the plurality bond pads, and then a second plurality of driver cells are placed to the inside of the plurality of bond pads.
    Type: Application
    Filed: August 9, 2005
    Publication date: December 8, 2005
    Inventor: Michael Jassowski
  • Patent number: 6784558
    Abstract: An embodiment of an integrated circuit die with staggered bond pads and optimized driver layout includes a staggered array of bond pads with an outer ring of bond pads and an inner ring of bond pads. Driver/ESD circuit cells for the outer ring of bond pads are located to the outside of the bond pads (between the outer ring of bond pads and the nearest die edge). The driver/ESD cells for the inner ring of bond pads are located to the inside of the bond pads (between the inner ring of bond pads and the die core). The integrated circuit die is coupled to a lead frame via bond wires.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventor: Michael A. Jassowski
  • Publication number: 20040056367
    Abstract: An embodiment of an integrated circuit die with staggered bond pads and optimized driver layout includes a staggered array of bond pads with an outer ring of bond pads and an inner ring of bond pads. Driver/ESD circuit cells for the outer ring of bond pads are located to the outside of the bond pads (between the outer ring of bond pads and the nearest die edge). The driver/ESD cells for the inner ring of bond pads are located to the inside of the bond pads (between the inner ring of bond pads and the die core). The integrated circuit die is coupled to a lead frame via bond wires.
    Type: Application
    Filed: July 11, 2003
    Publication date: March 25, 2004
    Inventor: Michael A. Jassowski
  • Patent number: 5798541
    Abstract: A layout arrangement which provides a contouring of cells that allows the individual rectangular cell boundaries to overlap each other to a point at which individual device edges abut one another thereby utilizing die area which is normally lost to use. In order to attain this result, a new cell contour boundary is described about each cell at the edge of each individual device adjacent the exterior of the cell at a distance at which other cells may abut without disturbing the operation of the cell. Then, computer implemented processes are applied to cause the cells to fit abutting the newly described boundaries.
    Type: Grant
    Filed: March 17, 1997
    Date of Patent: August 25, 1998
    Assignee: Intel Corporation
    Inventor: Michael Jassowski
  • Patent number: 5768146
    Abstract: A layout arrangement which provides a contouring of cells that allows the individual rectangular cell boundaries to overlap each other to a point at which individual device edges abut one another thereby utilizing die area which is normally lost to use. In order to attain this result, a new cell contour boundary is described about each cell at the edge of each individual device adjacent the exterior of the cell at a distance at which other cells may abut without disturbing the operation of the cell. Then, computer implemented processes are applied to cause the cells to fit abutting the newly described boundaries.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: June 16, 1998
    Assignee: Intel Corporation
    Inventor: Michael Jassowski
  • Patent number: 5668389
    Abstract: An arrangement for providing power to a semiconductor array of cells on a substrate in which the metal 2 power conductors are truncated into short lengths sufficient only to reach between the metal 1 power conductors of adjacent rows of cells, the metal 2 power conductors are placed under the metal 4 power conductors at each side to reduce the current through the metal 3 power conductors, and the metal 3 power conductors are narrowed to the level necessary to carry the reduced current and placed adjacent upper or lower edges of the cells. The arrangement increases the amount of space available for access to the external connection nodes of the devices in the cells of a group on a substrate while reducing the size of the metal overlays necessary to carry power to the cells.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: September 16, 1997
    Assignee: Intel Corporation
    Inventors: Michael Jassowski, Keith Smith
  • Patent number: 5641978
    Abstract: The I/O buffer layout of a pad-limited die comprises a pad ring having four partially-overlapping I/O-buffer arrays arranged in a pinwheel pattern at the periphery of a square die. To enable electrical interconnection of transversely-overlapping I/O buffers with the core logic of the die, overlapping I/O buffers of adjacent I/O-buffer arrays are separated by routing channels and the circuitry of longitudinally-overlapping buffers is abridged so that each of these buffers is capable of performing only a limited range of functions.
    Type: Grant
    Filed: July 7, 1995
    Date of Patent: June 24, 1997
    Assignee: Intel Corporation
    Inventor: Michael A. Jassowski