Abstract: A circuit for aligning the phase of a parallel data signal to a clock signal. The circuit includes a parallel data terminal for receiving a parallel data signal formed by multiple word bits, a clock terminal for receiving a clock signal, and a data ready terminal for receiving a data ready signal which has a logic state transition aligned with a first information bit of the parallel data signal. A plurality of data signal delay and sampling circuits connected to the clock terminal and the parallel data terminal provide time-slice bit samples of each information bit of the parallel data signal. A comparator and decision circuit coupled to the clock terminal and at least one of the data signal delay and sampling circuits compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal.

Abstract: A parallel, point-to-point bus architecture for interconnecting two or more electronic components for data communication. The bus architecture includes a non-blocking crosspoint switch having a tap for interconnection to each component, a clock terminal for receiving a common clock signal and an interface for connecting each component to a tap of the crosspoint switch. Each interface includes parallel data terminals for coupling data signals between the crosspoint switch tap and the component, a clock terminal for coupling the common clock signal between the crosspoint switch tap and the component and a clock-to-data alignment system. The clock-to-data alignment system aligns the data signals coupled between the crosspoint switch tap and the component to the common clock signal. Simultaneous data communications at very high speeds can be achieved through use of the bus.

Abstract: A circuit for aligning the phase of a parallel data signal to a clock signal. The circuit includes a parallel data terminal for receiving a parallel data signal formed by multiple word bits, a clock terminal for receiving a clock signal, and a data ready terminal for receiving a data ready signal which has a logic state transition aligned with a first information bit of the parallel data signal. A plurality of data signal delay and sampling circuits connected to the clock terminal and the parallel data terminal provide time-slice bit samples of each information bit of the parallel data signal. A comparator and decision circuit coupled to the clock terminal and at least one of the data signal delay and sampling circuits compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal.

Abstract: A parallel, point-to-point bus architecture for interconnecting two or more electronic components for data communication. The bus architecture includes a non-blocking crosspoint switch having a tap for interconnection to each component, a clock terminal for receiving a common clock signal and an interface for connecting each component to a tap of the crosspoint switch. Each interface includes parallel data terminals for coupling data signals between the crosspoint switch tap and the component, a clock terminal for coupling the common clock signal between the crosspoint switch tap and the component and a clock-to-data alignment system. The clock-to-data alignment system aligns the data signals coupled between the crosspoint switch tap and the component to the common clock signal. Simultaneous data communications at very high speeds can be achieved through use of the bus.

Abstract: A self-terminating FET digital logic receiver for impedance-matched interconnection to a transmission line having a uniform characteristic impedance. The receiver includes an input terminal, a current mirror formed by first and second FETs, and a load. First and second non-zero current level digital logic signals are received from the transmission line at the input terminal. The first current mirror FET is connected to the input terminal and configured to provide nonlinear current/voltage characteristics between the first and second current levels which approximate the characteristic impedance of the transmission line. Substantially all the current of the digital logic signals is therefore absorbed by the first FET to minimize signal reflections on the transmission line. The second FET is connected to the first FET to provide a mirror current having current levels proportional to the current levels of the digital logic signals.