Patents by Inventor Michael John Erickson
Michael John Erickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7089413Abstract: Techniques are disclosed for resetting agents in a computer system without requiring the computer system, or partitions thereof, to be reset. In one embodiment, each agent in the system is associated with a corresponding partition. A reset signal directed to an agent is redirected to a reset type selector which determines whether the partition associated with the agent is in a run state (an “unsafe run state”) in which resetting the agent will cause the partition to crash. If the partition is in an unsafe run state, a soft reset is performed on the agent. Otherwise, a hard reset is performed on the agent. If performing a soft reset does not solve the problem that was the impetus for the reset signal, the partition may be brought into a safe run state before performing a hard reset on it.Type: GrantFiled: March 5, 2003Date of Patent: August 8, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, David L. Tharp, Daniel V. Zilavy
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Patent number: 7065691Abstract: A computer system has at least one processor, a memory system, a Joint Test Action Group (JTAG) bus interface, and Input/Ouput devices. At least one Input/Ouput device of the system has an integrated circuit connected to and readable by the JTAG bus interface. The memory system of the computer system contains an exception handler capable of reading a state of the readable integrated circuit of the Input/Output device upon occurrence of an exception.Type: GrantFiled: May 19, 2003Date of Patent: June 20, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Paul John Mantey
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Patent number: 7039892Abstract: Systems, methods and software products ensure correct connectivity between circuit designs. A list of connections of the circuit designs is generated. One or more mapping files are generated from the list to correlate connections between the circuit designs. The mapping file is regenerated in response to modification of at least one of the circuit designs.Type: GrantFiled: August 19, 2003Date of Patent: May 2, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Paul John Mantey, John S. Atkinson, Michael John Erickson
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Patent number: 6961795Abstract: An apparatus and method for indicating and allowing hot swapping of a circuit board. During both insertion and extraction of a circuit board from a system, two inputs signals are generated from staggered pins located on the circuit board's connector. The inputs are processed through a NAND function implemented with transistors and output to two Schmitt trigger inverters connected in series. The output of the series connection of Schmitt trigger inverters goes high when both input signals are high and goes low when one of the inputs signals goes low. In addition, through the use of a resistor, capacitor combination connected to the input of the first Schmitt trigger inverter, the output signal remains high for a period of time after one of the input signals goes low. This additional period of time prevents any damage or disruption of signaling caused by transient current and voltage fluctuations as a circuit board is inserted or extracted.Type: GrantFiled: July 21, 2003Date of Patent: November 1, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Richard K. Brush
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Patent number: 6954929Abstract: The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and stored on a firmware server. The programmable parts are preferably integrated with the printed circuit boards; each of the boards networks to the firmware server by connection with an interface server, such that the image files download to the circuit board for programming the board's internal programmable parts. Networking between the parts and the firmware server can include communications across the Internet and/or one or more area networks. Multiple interface servers may be integral with the products incorporating the programmable parts so that many products may be updated concurrently.Type: GrantFiled: July 30, 2001Date of Patent: October 11, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, David R. Maciorowski, Christopher S Kroeger
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Patent number: 6915441Abstract: A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.Type: GrantFiled: July 30, 2001Date of Patent: July 5, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: David R. Macior wski, Michael John Erickson, Paul J. Mantey
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Patent number: 6914951Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.Type: GrantFiled: July 24, 2001Date of Patent: July 5, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Bradley D. Winick, David R. Maciorowski
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Patent number: 6898775Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.Type: GrantFiled: August 7, 2003Date of Patent: May 24, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Paul J. Mantey, John S Atkinson
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Patent number: 6883109Abstract: A method of updating programmable device configuration code stored in EEPROMs of a system is operable on complex systems having separate management and system processors. The method includes executing a sequence for updating programmable device configuration code on a management processor of the system including erasing the EEPROMs, writing at least one block of configuration code to the EEPROMs, and checking for errors after writing. The errors checked for include failure of a FIFO to empty. Upon detecting errors, the method includes automatically retrying writes. Embodiments of the method are operable on systems having multiple serial busses interconnecting EEPROMs to a common configuration logic, and on systems having multiple management processors each capable of accessing the common configuration logic.Type: GrantFiled: July 30, 2001Date of Patent: April 19, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Edward A Cross, David R. Maciorowski
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Publication number: 20040237011Abstract: A computer system has at least one processor, a memory system, a Joint Test Action Group (JTAG) bus interface, and Input/Ouput devices. At least one Input/Ouput device of the system has an integrated circuit connected to and readable by the JTAG bus interface. The memory system of the computer system contains an exception handler capable of reading a state of the readable integrated circuit of the Input/Output device upon occurrence of an exception.Type: ApplicationFiled: May 19, 2003Publication date: November 25, 2004Inventors: Michael John Erickson, Paul John Mantey
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Publication number: 20040225783Abstract: A bus bridge is capable of transferring information between a first serial bus and a target serial bus. The bridge is capable of operating as a bus slave on the first serial bus, and as a bus master on the target serial bus. The first serial bus in a particular embodiment is an IIC serial bus, while the target serial bus is a JTAG bus. There may be additional target serial busses, and there is a selection apparatus whereby commands may be directed to a particular target serial bus.Type: ApplicationFiled: July 30, 2001Publication date: November 11, 2004Inventors: Michael John Erickson, David R. MacIorowski, Paul John Mantey
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Patent number: 6807596Abstract: A system for removal and replacement of core I/O devices while the rest of the computer system is powered-up and operational. The system comprises a custom form-factor core I/O card that contains a plurality of I/O devices, including a processor for managing the card's I/O functions. A command is sent to an operating system, running on a system processor external to the core I/O card, that notifies the system to stop using, and de-configure, the hardware on the core I/O card. Once the OS receives this notification, an indication that the card is ready to be removed is sent to the user. The user then removes the card from its slot and inserts a replacement card into the same slot. The system software then discovers the I/O components on the core I/O card to determine what components are available, and then configures the new I/O device(s).Type: GrantFiled: July 26, 2001Date of Patent: October 19, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Daniel V. Zilavy, Bradley D. Winick, Paul J. Mantey
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Publication number: 20040177242Abstract: Techniques are disclosed for resetting agents in a computer system without requiring the computer system, or partitions thereof, to be reset. In one embodiment, each agent in the system is associated with a corresponding partition. A reset signal directed to an agent is redirected to a reset type selector which determines whether the partition associated with the agent is in a run state (an “unsafe run state”) in which resetting the agent will cause the partition to crash. If the partition is in an unsafe run state, a soft reset is performed on the agent. Otherwise, a hard reset is performed on the agent. If performing a soft reset does not solve the problem that was the impetus for the reset signal, the partition may be brought into a safe run state before performing a hard reset on it.Type: ApplicationFiled: March 5, 2003Publication date: September 9, 2004Inventors: Michael John Erickson, David L. Tharp, Daniel V. Zilavy
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Publication number: 20040104742Abstract: An apparatus and method for indicating and allowing hot swapping of a circuit board. During both insertion and extraction of a circuit board from a system, two inputs signals are generated from staggered pins located on the circuit board's connector. The inputs are processed through a NAND function implemented with transistors and output to two Schmitt trigger inverters connected in series. The output of the series connection of Schmitt trigger inverters goes high when both input signals are high and goes low when one of the inputs signals goes low. In addition, through the use of a resistor, capacitor combination connected to the input of the first Schmitt trigger inverter, the output signal remains high for a period of time after one of the input signals goes low. This additional period of time prevents any damage or disruption of signaling caused by transient current and voltage fluctuations as a circuit board is inserted or extracted.Type: ApplicationFiled: July 21, 2003Publication date: June 3, 2004Inventors: Michael John Erickson, Richard K. Brush
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Publication number: 20040034842Abstract: Systems, methods and software products ensure correct connectivity between circuit designs. A list of connections of the circuit designs is generated. One or more mapping files are generated from the list to correlate connections between the circuit designs. The mapping file is regenerated in response to modification of at least one of the circuit designs.Type: ApplicationFiled: August 19, 2003Publication date: February 19, 2004Inventors: Paul John Mantey, John S. Atkinson, Michael John Erickson
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Publication number: 20040031012Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.Type: ApplicationFiled: August 7, 2003Publication date: February 12, 2004Inventors: Michael John Erickson, Paul J. Mantey, John S. Atkinson
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Patent number: 6629307Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.Type: GrantFiled: July 24, 2001Date of Patent: September 30, 2003Assignee: Hewlett-Packard Development Company, LP.Inventors: Michael John Erickson, Paul J. Mantey, John S Atkinson
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Patent number: 6625681Abstract: An apparatus and method for indicating and allowing hot swapping of a circuit board. During both insertion and extraction of a circuit board from a system, two inputs signals are generated from staggered pins located on the circuit board's connector. The inputs are processed through a NAND function implemented with transistors and output to two Schmitt trigger inverters connected in series. The output of the series connection of Schmitt trigger inverters goes high when both input signals are high and goes low when one of the inputs signals goes low. In addition, through the use of a resistor, capacitor combination connected to the input of the first Schmitt trigger inverter, the output signal remains high for a period of time after one of the input signals goes low. This additional period of time prevents any damage or disruption of signaling caused by transient current and voltage fluctuations as a circuit board is inserted or extracted.Type: GrantFiled: March 29, 1999Date of Patent: September 23, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael John Erickson, Richard K. Brush
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Publication number: 20030126473Abstract: A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.Type: ApplicationFiled: July 30, 2001Publication date: July 3, 2003Inventors: David R. Maciorowski, Michael John Erickson, Paul J. Mantey
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Publication number: 20030065916Abstract: The invention provides methods and logic for determining the source of a processor reset in a system having a processor and a plurality of processor reset sources. The plurality of processor reset sources couple to a corresponding plurality of RS latches. One of the RS latches sets in response to a processor reset generated by one of the processor resets. That one RS latch writes logic high to a dedicated register of a read register. After rebooting, the processor reads the read register to determine which register is logic high, corresponding to the source that generated the reset. The read register is reset by writing logic high into a write register, thereby resetting the set RS latch and clearing the logic high register of the read register. The processor writes logic low to all write register bits to clear enable the RS latches so that subsequent processor resets are identified.Type: ApplicationFiled: July 30, 2001Publication date: April 3, 2003Inventors: Michael John Erickson, David R. Maciorowski