Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.

Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.

Abstract: A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.

Abstract: A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core of the plurality of cores and assigns a second subset of the image rendering tasks to a second core of the plurality of cores. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.

Abstract: A technique for rendering is provided. The technique includes for a set of primitives processed in a coarse binning pass, outputting early draw data to an early draw buffer; while processing the set of primitives in the coarse binning pass, processing the early draw data in a fine binning pass; and processing remaining primitives of the set of primitives in the fine binning pass.

Abstract: A system and method for coherency gathering for rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes including upper level nodes and lower level nodes. For each instance where one of the lower level nodes is a child of one of the upper level nodes, an instance transform is defined, specifying the relationship between a first coordinate system of the upper level node and the second coordinate system for that instance of the lower level node. The system provides an instance transform cache for storing a plurality of these instance transforms while conducting intersection testing.

Abstract: A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. First cores are configured to process groups of primitives, to produce transformed geometry data. The graphics rendering system uses at least one virtualised memory space. At least one virtualised memory space is segmented such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the index. The top level of the hierarchical index is pre-allocated, and each core is primed by providing it with said top level of the hierarchical index.

Abstract: A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. The graphics rendering system uses at least one virtualised memory space. A hierarchical index is provided, to index the physical memory portions associated with virtual memory portions in the at least one virtualised memory space. The portions of memory allocated for the hierarchical index are recorded in an MMU (memory management unit) list (MLIST). The MLIST comprises a plurality of entries, each entry being associated with a respective portion of the hierarchical index, wherein each entry includes an indication of the portion of virtual memory that is indexed by that portion of the hierarchical index. The MLIST is used to identify, and free, portions of memory associated with indexing virtual memory that has been fully consumed in a partial render.

Abstract: A multicore graphics rendering system includes a plurality of cores implementing tile-based deferred rendering of a stream of primitives. First cores perform geometry processing on groups of primitives. Each group of primitives is associated with a group index denoting its position in the stream of primitives. Each first core produces a set of tile control lists. Each tile control list produced by each first core describes the primitives processed by that first core that are present in the respective tile. Second cores perform fragment processing for one or more tiles. Each second core is configured to read, from a memory, the tile control lists produced for a given tile by the various first cores, and to stitch together these tile control lists to produce a combined tile control stream for the tile. The contents of the tile control lists are stitched together in the order defined by the group indices.

Abstract: A multicore graphics rendering system is disclosed, comprising a plurality of cores configured to implement tile-based rendering of a stream of primitives. First cores are configured to process groups of primitives, to produce transformed geometry data. The transformed geometry data describes, for each of a plurality of tiles, the primitives processed by each first core that are present in that tile, each group being associated with a group index. The group indices define the ordering of the groups in the stream of primitives. An allocation list (ALIST) stores, for each portion of memory written to by the first cores, an indication of a part of the frame with which that portion is associated, and the latest group index of the transformed geometry data written to the portion. The ALIST is used to identify, and free, portions of memory that have been fully consumed in a partial render.

Abstract: A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include performing two-level primitive batch binning in parallel across multiple rendering engines, wherein tiles for subdividing coarse-level work across the rendering engines have the same size as tiles for performing coarse binning.

Abstract: A system and method for coherency gathering for rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes including upper level nodes and lower level nodes. For each instance where one of the lower level nodes is a child of one of the upper level nodes, an instance transform is defined, specifying the relationship between a first coordinate system of the upper level node and the second coordinate system for that instance of the lower level node. The system provides an instance transform cache for storing a plurality of these instance transforms while conducting intersection testing.

Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.

Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.

Abstract: A processor includes a blocking circuit between an upstream section and a downstream section of a hardware pipeline, and control circuitry which triggers the upstream section to process an upstream phase of a first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed in a downstream phase of the first task. In response to detecting that the upstream section has finished processing the upstream phase of the first task, the control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the downstream phase of the first task, and switches the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing to the downstream section.