Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.

Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.

Abstract: A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.

Abstract: An implementation comprises traversing a bounding volume hierarchy for each ray of a plurality of rays concurrently using a plurality of execution items. In response to determining that a first execution item of the plurality of execution items is finished traversing the bounding volume hierarchy for a first ray of the plurality rays, the embodiment causes the first execution item to traverse the bounding volume hierarchy for a second ray of the plurality of rays while a second execution item of the plurality of execution items traverses the bounding volume hierarchy for the second ray. And the embodiment comprises initiating side-effects with the first and second execution items in an order indicated by the bounding volume hierarchy.

Abstract: A technique for performing ray tracing operations is provided. The technique includes identifying triangles to include in a compressed triangle block; storing data common to the identified triangles as common data of the compressed triangle block; and storing data unique to the identified triangles as unique data of the compressed triangle block.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, testing a plurality of bounding boxes for intersection with a ray in parallel, wherein the plurality of bounding boxes are specified by a plurality of box data items of a parent box node of a bounding volume hierarchy; determining that, for a first child node that is pointed to by a two or more node pointers specified by two or more box data items of the plurality of box data items, at least one bounding box specified by the two or more box data items is intersected by the ray; and in response to the determining, traversing to the first child node.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in a first iteration of a ray traversal technique, traversing to an instance node of a bounding volume hierarchy; in a second iteration of the ray traversal technique that is subsequent to the first iteration, transforming a ray based on an instance transform of the instance node to generate a transformed ray; and in the second iteration, performing a ray-box intersection test for box node data of the instance node based on the transformed ray.

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.

Abstract: A processor and a method of obtaining data for a processor are provided. The processor comprises at least a first core, a second core, and a distributed cache. The distributed cache comprises a first cache slice connected to the first core and a second cache slice connected to the second core and to the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice.

Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.

Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.

Abstract: A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.

Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.

Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.

Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.

Abstract: A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core of the plurality of cores and assigns a second subset of the image rendering tasks to a second core of the plurality of cores. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.

Abstract: A technique for rendering is provided. The technique includes for a set of primitives processed in a coarse binning pass, outputting early draw data to an early draw buffer; while processing the set of primitives in the coarse binning pass, processing the early draw data in a fine binning pass; and processing remaining primitives of the set of primitives in the fine binning pass.

Abstract: A system and method for coherency gathering for rays in a ray tracing system. The ray tracing system uses a hierarchical acceleration structure comprising a plurality of nodes including upper level nodes and lower level nodes. For each instance where one of the lower level nodes is a child of one of the upper level nodes, an instance transform is defined, specifying the relationship between a first coordinate system of the upper level node and the second coordinate system for that instance of the lower level node. The system provides an instance transform cache for storing a plurality of these instance transforms while conducting intersection testing.

Abstract: A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. The graphics rendering system uses at least one virtualised memory space. A hierarchical index is provided, to index the physical memory portions associated with virtual memory portions in the at least one virtualised memory space. The portions of memory allocated for the hierarchical index are recorded in an MMU (memory management unit) list (MLIST). The MLIST comprises a plurality of entries, each entry being associated with a respective portion of the hierarchical index, wherein each entry includes an indication of the portion of virtual memory that is indexed by that portion of the hierarchical index. The MLIST is used to identify, and free, portions of memory associated with indexing virtual memory that has been fully consumed in a partial render.

Abstract: A multicore graphics rendering system includes a plurality of cores configured to implement tile-based rendering of a stream of primitives. First cores are configured to process groups of primitives, to produce transformed geometry data. The graphics rendering system uses at least one virtualised memory space. At least one virtualised memory space is segmented such that the first cores are allocated respective non-overlapping virtual address ranges in the space, the virtual address ranges being associated with different entries in a top level of the index. The top level of the hierarchical index is pre-allocated, and each core is primed by providing it with said top level of the hierarchical index.