Patents by Inventor Michael John Livesley

Michael John Livesley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111587
    Abstract: Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. Because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Andrew Erin Kensler, Sean Keely, Michael John Livesley, David William John Pankratz
  • Publication number: 20250111586
    Abstract: A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michael John Livesley, David William John Pankratz, Sean Keely, Andrew Erin Kensler
  • Patent number: 12266044
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Grant
    Filed: December 31, 2023
    Date of Patent: April 1, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Patent number: 12243119
    Abstract: A graphics processor including geometry and fragment processing logic, and a memory manager arranged to allocate and deallocate memory for use to hold tile data. The memory manager tracks which memory regions are allocated to hold tile data of which subdivisions (e.g. macrotiles) of the render area. Once the fragment processing logic has finished processing the tile data of a subdivision, it sends an identifier of that subdivision to the memory manager for deallocation. The processor further comprises a blocking circuit enabling the fragment processing logic to start processing tile data of a second task while the memory manager is still deallocating some of the memory regions allocated to the subdivisions of a first task; by preventing identifiers of subdivisions of the second task being passed to the memory manager until it has completed deallocating the memory regions allocated to the first task.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 4, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Michael John Livesley, Ian King, Alistair Goudie
  • Patent number: 12205193
    Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: January 21, 2025
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ruijin Wu, Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi
  • Publication number: 20240427632
    Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.
    Type: Application
    Filed: September 6, 2024
    Publication date: December 26, 2024
    Inventors: Michael John Livesley, Ian King, Alistair Goudie
  • Patent number: 12112197
    Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: October 8, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Michael John Livesley, Ian King, Alistair Goudie
  • Publication number: 20240231914
    Abstract: A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 11, 2024
    Inventor: Michael John Livesley
  • Publication number: 20240212259
    Abstract: An implementation comprises traversing a bounding volume hierarchy for each ray of a plurality of rays concurrently using a plurality of execution items. In response to determining that a first execution item of the plurality of execution items is finished traversing the bounding volume hierarchy for a first ray of the plurality rays, the embodiment causes the first execution item to traverse the bounding volume hierarchy for a second ray of the plurality of rays while a second execution item of the plurality of execution items traverses the bounding volume hierarchy for the second ray. And the embodiment comprises initiating side-effects with the first and second execution items in an order indicated by the bounding volume hierarchy.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, Daniel James Skinner, Michael John Livesley
  • Publication number: 20240203032
    Abstract: A technique for performing ray tracing operations is provided. The technique includes identifying triangles to include in a compressed triangle block; storing data common to the identified triangles as common data of the compressed triangle block; and storing data unique to the identified triangles as unique data of the compressed triangle block.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, David Ronald Oldcorn, Daniel James Skinner, Michael John Livesley, David Kirk McAllister
  • Publication number: 20240203033
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, in a first iteration of a ray traversal technique, traversing to an instance node of a bounding volume hierarchy; in a second iteration of the ray traversal technique that is subsequent to the first iteration, transforming a ray based on an instance transform of the instance node to generate a transformed ray; and in the second iteration, performing a ray-box intersection test for box node data of the instance node based on the transformed ray.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, David Kirk McAllister, David Ronald Oldcorn, Michael John Livesley, Daniel James Skinner
  • Publication number: 20240203034
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, testing a plurality of bounding boxes for intersection with a ray in parallel, wherein the plurality of bounding boxes are specified by a plurality of box data items of a parent box node of a bounding volume hierarchy; determining that, for a first child node that is pointed to by a two or more node pointers specified by two or more box data items of the plurality of box data items, at least one bounding box specified by the two or more box data items is intersected by the ray; and in response to the determining, traversing to the first child node.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, David Kirk McAllister, Daniel James Skinner, Michael John Livesley, David Ronald Oldcorn
  • Publication number: 20240169641
    Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include providing indices and vertices to a culling shader; culling primitives and outputting primitives and indices that are not culled; and generating information for a fine binning pass based on the indices and primitives that are not culled.
    Type: Application
    Filed: March 31, 2023
    Publication date: May 23, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vishrut Vaibhav, Michael John Livesley, Tad Robert Litwiller
  • Publication number: 20240160571
    Abstract: A processor and a method of obtaining data for a processor are provided. The processor comprises at least a first core, a second core, and a distributed cache. The distributed cache comprises a first cache slice connected to the first core and a second cache slice connected to the second core and to the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice.
    Type: Application
    Filed: September 29, 2023
    Publication date: May 16, 2024
    Inventors: Mark Landers, Ian King, Alistair Goudie, Michael John Livesley
  • Publication number: 20240135625
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Application
    Filed: December 31, 2023
    Publication date: April 25, 2024
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley
  • Publication number: 20240104685
    Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ruijin Wu, Michael John Livesley, Kiia Kallio, Jan H. Achrenius, Mika Tuomi
  • Patent number: 11934878
    Abstract: A method and apparatus are provided for allocating memory for geometry processing in a 3-D graphics rendering system comprising multiple cores. Geometry processing work is divided up into discrete work-packages, which form an ordered sequence. Cores are assigned different work-packages to process, and make memory allocation requests to enable them to store the results of the processing. Memory allocation requests relating to the current earliest uncompleted work-package in the sequence are treated differently to other requests, and may be prioritised.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: March 19, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Michael John Livesley
  • Publication number: 20240070961
    Abstract: Techniques for performing rendering operations are disclosed herein. The techniques include in a coarse binning pass, generating a sorted set of draw calls, based on geometry processed through a world space pipeline and vertex indices obtained from an input assembler.
    Type: Application
    Filed: December 27, 2022
    Publication date: February 29, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Michael John Livesley, Vishrut Vaibhav, Tad Robert Litwiller
  • Patent number: 11908065
    Abstract: A technique for performing ray tracing operations is provided. The technique includes, in response to detecting that a threshold number of traversal stage work-items of a wavefront have terminated, increasing intersection test parallelization for non-terminated work-items.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 20, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Daniel James Skinner, Michael John Livesley, David William John Pankratz
  • Patent number: 11861782
    Abstract: Data structures, methods and tiling engines for storing tiling data in memory wherein the tiles are grouped into tile groups and the primitives are grouped into primitive blocks. The methods include, for each tile group: determining, for each tile in the tile group, which primitives of each primitive block intersect that tile; storing in memory a variable length control data block for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group; and storing in memory a control stream comprising a fixed sized primitive block entry for each primitive block that comprises at least one primitive that intersects at least one tile of the tile group, each primitive block entry identifying a location in memory of the control data block for the corresponding primitive block. Each primitive block entry may comprise valid tile information identifying which tiles of the tile group are valid for the corresponding primitive block.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: January 2, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Robert Brigg, Michael John Livesley