Patents by Inventor Michael John Mayfield
Michael John Mayfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7305526Abstract: Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.Type: GrantFiled: November 5, 2004Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: Michael Thomas Benhase, Robert Alan Cargnoni, James Stephen Fields, Jr., Michael John Mayfield, Bruce Mealey
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Patent number: 7171445Abstract: An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.Type: GrantFiled: January 7, 2002Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: James W. Allen, Michael John Mayfield, Alvan Wing Ng
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Patent number: 6968431Abstract: In a multiprocessor system using snooping protocols, system command conflicts are prevented by comparing processor commands with prior snoops within a specified time defined window. A determination is then made as to whether a command issued by a given processor is likely to cause a system conflict with another command issued within said specified time defined window. If so, the time of execution of any such snoop command determined as being likely to cause a system conflict is delayed. This approach uses address bus arbitration rules to prevent system livelocks due to both coherency and resource conflicts.Type: GrantFiled: November 15, 2001Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventor: Michael John Mayfield
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Patent number: 6915415Abstract: A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.Type: GrantFiled: January 7, 2002Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray
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Publication number: 20030131138Abstract: An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses substantially at the same time by delaying data transmitted over faster busses before the data is provided to a local logic at a receiving end of the faster busses. The interfacing logic comprises two or more paths of a multiplexer component connected to a storage component. The storage components are connected to another multiplexer component for selecting one of the two or more paths. Preferably, a bus control logic in the receiving end determines how much delay is performed to compensate for delay differences between data busses.Type: ApplicationFiled: January 7, 2002Publication date: July 10, 2003Applicant: International Business Machines CorporationInventors: James W. Allen, Michael John Mayfield, Alvan Wing Ng
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Publication number: 20030131218Abstract: A method and apparatus for mapping some software prefetch instructions in a microprocessor system to a modified set of hardware prefetch instructions and executing the software prefetch by invoking the corresponding modified hardware prefetch instruction. For common software prefetch access patterns, by mapping the software prefetches to hardware, improved prefetching can be achieved without the need for additional hardware.Type: ApplicationFiled: January 7, 2002Publication date: July 10, 2003Applicant: International Business Machines CorporationInventors: Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray
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Patent number: 6587930Abstract: A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions.Type: GrantFiled: September 23, 1999Date of Patent: July 1, 2003Assignee: International Business Machines CorporationInventors: Sanjay Raghunath Deshpande, Peter Steven Lenk, Michael John Mayfield
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Publication number: 20030120874Abstract: A distributed system structure for a large-way, multi-bus, multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The system allows for the implementation of a bus protocol that reports the state of a cache line to a master device along with the first beat of data delivery for a cacheable coherent Read. Since the achievement of coherency is distributed in time and space, the issue of data integrity is addressed through a variety of actions.Type: ApplicationFiled: January 17, 2003Publication date: June 26, 2003Inventors: Sanjay Raghunath Deshpande, Peter Steven Lenk, Michael John Mayfield
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Patent number: 6578130Abstract: A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.Type: GrantFiled: October 18, 2001Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventors: Brian David Barrick, Michael John Mayfield, Brian Patrick Hanley
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Patent number: 6574712Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction is used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine. The instruction also limits the amount of data to be prefetched.Type: GrantFiled: April 14, 2000Date of Patent: June 3, 2003Assignee: International Business Machines CorporationInventors: James Allan Kahle, Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray, Edward John Silha, Joel M. Tendler
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Publication number: 20030101297Abstract: An apparatus and method for preventing livelocks in a switched system with a switch, a distributed bus arbiter, a plurality of microprocessors, busses and associated bus request logic, comprising said system. The method comprises generating a plurality of requests, defining times between the requests, generating retries of the switches, and varying within the bus request logic, time as a function of the switch retries.Type: ApplicationFiled: November 29, 2001Publication date: May 29, 2003Applicant: International Business Machines CorporationInventors: James W. Allen, Michael John Mayfield, Alvan Wing Ng
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Publication number: 20030093657Abstract: In a multiprocessor system using snooping protocols, system command conflicts are prevented by comparing processor commands with prior snoops within a specified time defined window. A determination is then made as to whether a command issued by a given processor is likely to cause a system conflict with another command issued within said specified time defined window. If so, the time of execution of any such snoop command determined as being likely to cause a system conflict is delayed. This approach uses address bus arbitration rules to prevent system livelocks due to both coherency and resource conflicts.Type: ApplicationFiled: November 15, 2001Publication date: May 15, 2003Applicant: International Business Machines CorporationInventor: Michael John Mayfield
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Publication number: 20030079089Abstract: A method and apparatus for prefetching data in computer systems that tracks the number of prefetches currently active and compares that number to a preset maximum number of allowable prefetches to determine if additional prefetches should currently be performed. By limiting the number of prefetches being performed at any given time, the use of system resources for prefetching can be controlled, and thus system performance can be optimized.Type: ApplicationFiled: October 18, 2001Publication date: April 24, 2003Applicant: International Business Machines CorporationInventors: Brian David Barrick, Michael John Mayfield, Brian Patrick Hanley
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Patent number: 6535962Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.Type: GrantFiled: November 8, 1999Date of Patent: March 18, 2003Assignee: International Business Machines CorporationInventors: Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray
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Patent number: 6460115Abstract: A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.Type: GrantFiled: November 8, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: James Allan Kahle, Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray, Edward John Silha, Joel Tendler
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Patent number: 6446170Abstract: A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit.Type: GrantFiled: January 19, 1999Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Kin Shing Chan, Dwain Alan Hicks, Michael John Mayfield, Shih-Hsiung Stephen Tung
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Patent number: 6446167Abstract: A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. The prefetch request may include a signal notifying the third level cache to also prefetch.Type: GrantFiled: November 8, 1999Date of Patent: September 3, 2002Assignee: International Business Machines CorporationInventors: Michael John Mayfield, Francis Patrick O'Connell, David Scott Ray
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Patent number: 6298417Abstract: A deallocation pipelining circuit for use in a cache memory subsystem. The pipelining circuit is configured to initiate a storeback buffer (SBB) transfer of first line data stored in a first line of a cache memory array if the deallocation pipelining circuit detects a cache miss signal corresponding to the first line and identifies the first line data as modified data. The deallocation pipelining circuit is configured to issue a storeback request signal to a bus interface unit after the completion of the SBB transfer. The circuit initiates a bus interface unit transfer of the first line data after receiving a data acknowledge signal from the bus interface unit. The pipelining circuit is still further configured to deallocate the first line of the cache memory after receiving a request acknowledge signal from the bus interface unit.Type: GrantFiled: November 20, 1998Date of Patent: October 2, 2001Assignee: International Business Machines CorporationInventors: Kin Shing Chan, Dwain Alan Hicks, Michael John Mayfield, Shih-Hsiung Stephen Tung
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Patent number: 6202128Abstract: An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration.Type: GrantFiled: March 11, 1998Date of Patent: March 13, 2001Assignee: International Business Machines CorporationInventors: Kin Shing Chan, Dwain Alan Hicks, Peichun Peter Liu, Michael John Mayfield, Shih-Hsiung Stephen Tung
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Patent number: 6085291Abstract: Within a data processing system implementing primary and secondary caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. Prefetching may be performed on cache misses or hits. Cache misses on successive cache lines may allocate a stream of cache lines to the stream buffers. Control circuitry, coupled to a stream filter circuit, selectively controls fetching and prefetching of data from system memory to the primary and secondary caches associated with a processor and to a stream buffer circuit.Type: GrantFiled: November 6, 1995Date of Patent: July 4, 2000Assignee: International Business Machines CorporationInventors: Dwain Alan Hicks, Michael John Mayfield, David Scott Ray, Shih-Hsiung Stephen Tung