Patents by Inventor Michael John Seddon

Michael John Seddon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10403544
    Abstract: Implementations of a method of singulating a plurality of die may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer only from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a backgrinding tape. The method may also include thinning a second side of the semiconductor wafer to a predetermined distance to the depth of the plurality of trenches to singulate the plurality of die.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John Seddon
  • Publication number: 20190080965
    Abstract: Implementations of a method of singulating a plurality of die may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer only from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a backgrinding tape. The method may also include thinning a second side of the semiconductor wafer to a predetermined distance to the depth of the plurality of trenches to singulate the plurality of die.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 14, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John SEDDON
  • Patent number: 10083868
    Abstract: Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: September 25, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John Seddon
  • Publication number: 20180233411
    Abstract: Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.
    Type: Application
    Filed: April 17, 2018
    Publication date: August 16, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John SEDDON
  • Patent number: 9991164
    Abstract: Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: June 5, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John Seddon
  • Publication number: 20170372962
    Abstract: Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first side of the semiconductor wafer where the plurality of die include a desired thickness. The method may include etching a plurality of trenches into the semiconductor wafer from the first side of the semiconductor wafer where the plurality of trenches is located adjacent to a perimeter of the plurality of die. A depth of the plurality of trenches may be greater than the desired thickness of the plurality of die. The method may also include mounting the first side of the semiconductor wafer to a tape, thinning a second side of the semiconductor wafer, exposing the plurality of trenches while thinning the second side, and singulating the plurality of die through exposing the plurality of trenches.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 28, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael John SEDDON
  • Patent number: 6376266
    Abstract: A semiconductor package (8) with a die (10) having die pads (16) coupled to inner ends (22) of interconnects (20), the die (10) and the interconnects (20) are molded in mold compound (30) with mounting surface (12) and outer ends (24) exposed. A semiconductor die has an interconnect surface opposite the mounting surface.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: April 23, 2002
    Assignee: Semiconductor Components Industries LLC
    Inventors: James Price Letterman, Jr., Kenneth Teik Kheong Low, Saat Shukri Embong, Chee Hiong Chew, Boon Huat Lim, Aik Chong Tan, Albert Laninga, Santhiragasen al sengram Pillay, Michael John Seddon, Brian Webb