Abstract: A device includes an amplifying device that when in operation transmits a data signal and a reference signal to a decision feedback equalizer (DFE) circuit. The amplifying device includes a variable gain amplifier (VGA) that when in operation generates the reference signal as having a predetermined gain relative to a received input signal and a continuous-time linear equalizer (CTLE) that operate to mitigate inter-symbol interference (ISI) on the data signal from a data stream comprising the data signal. The device further includes correction circuitry coupled to the amplifying device, wherein the correction circuitry when in operation mitigates variation in the predetermined gain of the VGA or variation in an output common-mode voltage of the VGA.

Abstract: A memory device includes a resistor string digital to analog convertor (DAC) configured to supply one or more offset voltages to a decision feedback equalizer (DFE) based on high and low bias voltages. The memory device also includes bias voltage generation circuitry configured to generate a reference current based on an offset voltage range trim, to generate a first correction current based on a detected temperature change, generate a second correction current based on a supplied voltage, the reference voltage of the memory device, and a supply correction trim, to generate an adjusted reference current based on the reference current, the first correction current, and the second correction current, to generate the high bias voltage based on the adjusted reference current, to generate the low bias voltage based on the reference current, and to supply the high bias voltage and the low bias voltage to the resistor string DAC.

Abstract: A device includes an amplifying device that when in operation transmits a data signal and a reference signal to a decision feedback equalizer (DFE) circuit. The amplifying device includes a variable gain amplifier (VGA) that when in operation generates the reference signal as having a predetermined gain relative to a received input signal and a continuous-time linear equalizer (CTLE) that operate to mitigate inter-symbol interference (IR) on the data signal from a data stream comprising the data signal. The device further includes correction circuitry coupled to the amplifying device, wherein the correction circuitry when in operation mitigates variation in the predetermined gain of the VGA or variation in an output common-mode voltage of the VGA.

Abstract: A device includes an amplifying device that when in operation transmits a data signal and a reference signal to a decision feedback equalizer (DFE) circuit. The amplifying device includes a variable gain amplifier (VGA) that when in operation generates the reference signal as having a predetermined gain relative to a received input signal and a continuous-time linear equalizer (CTLE) that operate to mitigate inter-symbol interference (IR) on the data signal from a data stream comprising the data signal. The device further includes correction circuitry coupled to the amplifying device, wherein the correction circuitry when in operation mitigates variation in the predetermined gain of the VGA or variation in an output common-mode voltage of the VGA.

Abstract: An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

Abstract: An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

Abstract: In an actuator driver array, each actuator driver includes a transition stage to initiate a state change of a driver output signal, a static stage to maintain the state change, and an isolation resistor to couple the driver output signal to an output node of the actuator driver during a static mode. In an array of pad capacitors, each pad capacitor has: a first terminal at a connector pad communicatively coupled to the output node; and a second terminal coupled to an RF ground rail. The isolation resistor and the pad capacitor form a low-pass filter to filter RF harmonics from a respective actuator driver to respective actuator circuitry, and to filter RF energy generated outside of the respective actuator driver to its output node. In an RF actuator array, a state of each element is controllable by a corresponding actuator driver in the actuator driver array.

Abstract: In an actuator driver array, each actuator driver includes a transition stage to initiate a state change of a driver output signal, a static stage to maintain the state change, and an isolation resistor to couple the driver output signal to an output node of the actuator driver during a static mode. In an array of pad capacitors, each pad capacitor has: a first terminal at a connector pad communicatively coupled to the output node; and a second terminal coupled to an RF ground rail. The isolation resistor and the pad capacitor form a low-pass filter to filter RF harmonics from a respective actuator driver to respective actuator circuitry, and to filter RF energy generated outside of the respective actuator driver to its output node. In an RF actuator array, a state of each element is controllable by a corresponding actuator driver in the actuator driver array.

Abstract: A circuit includes a regulation control circuit. The regulation control circuit includes an error amplifier to generate a control output signal based on an error signal input and a reference input. The regulation control circuit includes a level shifter to receive a negative voltage supplied to a load and to provide a positive error signal to the error signal input of the error amplifier. A driver circuit receives the control output signal from the error amplifier and generates a drive output signal in response to the control output signal. A regulation output circuit regulates the negative voltage supplied to the load in response to the drive output signal from the driver circuit.

Abstract: In an actuator driver array, each actuator driver includes a transition stage to initiate a state change of a driver output signal, a static stage to maintain the state change, and an isolation resistor to couple the driver output signal to an output node of the actuator driver during a static mode. In an array of pad capacitors, each pad capacitor has: a first terminal at a connector pad communicatively coupled to the output node; and a second terminal coupled to an RF ground rail. The isolation resistor and the pad capacitor form a low-pass filter to filter RF harmonics from a respective actuator driver to respective actuator circuitry, and to filter RF energy generated outside of the respective actuator driver to its output node. In an RF actuator array, a state of each element is controllable by a corresponding actuator driver in the actuator driver array.

Abstract: A circuit includes a regulation control circuit. The regulation control circuit includes an error amplifier to generate a control output signal based on an error signal input and a reference input. The regulation control circuit includes a level shifter to receive a negative voltage supplied to a load and to provide a positive error signal to the error signal input of the error amplifier. A driver circuit receives the control output signal from the error amplifier and generates a drive output signal in response to the control output signal. A regulation output circuit regulates the negative voltage supplied to the load in response to the drive output signal from the driver circuit.

Abstract: In described examples, a multi-stage charge pump includes first, second and third charge pump stages connected in series. Each of the first, second and third charge pump stages includes a charge pump circuit of a first type that increases an input signal of a respective charge pump circuit by up to a given amount. The multi-stage charge pump also includes a level shifter that swings a level clock signal between a voltage of an output signal of the third charge pump stage and one of an offset voltage and ground. The multi-stage charge pump further includes a charge pump circuit of a second type that increases the voltage of the output of the third charge pump stage by up to another amount and provides an output and the other amount is set by the level shifter. Also, the multi-stage charge pump includes a charge pump circuit of a third type.

Abstract: In described examples, a multi-stage charge pump includes first, second and third charge pump stages connected in series. Each of the first, second and third charge pump stages includes a charge pump circuit of a first type that increases an input signal of a respective charge pump circuit by up to a given amount. The multi-stage charge pump also includes a level shifter that swings a level clock signal between a voltage of an output signal of the third charge pump stage and one of an offset voltage and ground. The multi-stage charge pump further includes a charge pump circuit of a second type that increases the voltage of the output of the third charge pump stage by up to another amount and provides an output and the other amount is set by the level shifter. Also, the multi-stage charge pump includes a charge pump circuit of a third type.

Abstract: In an actuator driver array, each actuator driver includes a transition stage to initiate a state change of a driver output signal, a static stage to maintain the state change, and an isolation resistor to couple the driver output signal to an output node of the actuator driver during a static mode. In an array of pad capacitors, each pad capacitor has: a first terminal at a connector pad communicatively coupled to the output node; and a second terminal coupled to an RF ground rail. The isolation resistor and the pad capacitor form a low-pass filter to filter RF harmonics from a respective actuator driver to respective actuator circuitry, and to filter RF energy generated outside of the respective actuator driver to its output node. In an RF actuator array, a state of each element is controllable by a corresponding actuator driver in the actuator driver array.

Abstract: A dual-mode driver includes a transition stage and a static stage. The transition stage switches a bias voltage or an RF ground potential to an output pad to change the state of an RF actuator device connected at the output pad. After waiting a predetermined period of time for the RF actuator device to change state, the transition stage of the driver is disabled. A high-side or low-side static stage transistor maintains the driver output state through an isolation resistor. The isolation resistor and a capacitor formed at the driver output pad form an RC low-pass filter to block spurious noise generated at the driver. The RC filter also blocks RF energy that might otherwise enter the actuator driver from the actuator. Some embodiments also include a second RC filter located proximate to the output pad to prevent RF energy generated in the RF actuator from entering the driver.

Abstract: A dual-mode driver includes a transition stage and a static stage. The transition stage switches a bias voltage or an RF ground potential to an output pad to change the state of an RF actuator device connected at the output pad. After waiting a predetermined period of time for the RF actuator device to change state, the transition stage of the driver is disabled. A high-side or low-side static stage transistor maintains the driver output state through an isolation resistor. The isolation resistor and a capacitor formed at the driver output pad form an RC low-pass filter to block spurious noise generated at the driver. The RC filter also blocks RF energy that might otherwise enter the actuator driver from the actuator. Some embodiments also include a second RC filter located proximate to the output pad to prevent RF energy generated in the RF actuator from entering the driver.

Abstract: A power recycle circuit is for use in a power management system. An input of the power recycle circuit is for receiving a clock signal. A detection circuit is for sensing a minimum disable pulse when a clock signal is received and when a clock signal is not received. A power recycle circuit is for generating a power recycle signal in response to the minimum disable pulse. A state machine is for holding the power recycle signal for at least two clock cycles.

Abstract: An electronic system is provided that includes a plurality of power consuming electronic circuits and a power management system that interfaces a power supply to the plurality of power consuming electronic circuits. The power management system includes a power level detect circuit that includes a voltage level detector circuit that receives an analog voltage level signal indicative of a level of voltage provided from the power supply. The power level detect circuitry also includes digital encoding circuitry that encodes the analog voltage level signal as a digital powered level signal also indicative of the level of the power supply voltage. Each of the power consuming electronic circuit includes configuration circuitry to receive the digital power level signal and to configure operation of that particular power consuming electronic circuit responsive to the digital power level signal.

Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interface circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.

Abstract: A power management system is disclosed. The system includes an oscillator interface for use in a power management system, a power recycle circuit for use in a power management system, a pad clock and self test for use in a power management system, a clock enable circuit for use in a power management system, a power level detect circuit for use in a power management system, an internal source clock generation circuit for use in a power management system, and a power-save mode change detection circuit for use in a power management system. The oscillator interface includes an interle circuit for interfacing with an external oscillator used as a source of oscillations. A clock stabilization filter masks out spurious crystal frequencies in the oscillations during start-up of the power management system following an enabling of a feedback loop. The clock stabilization filter has circuitry which provides that the oscillations will start with a rising transition after filtering.