Patents by Inventor Michael Jonathan Thyer
Michael Jonathan Thyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11022647Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.Type: GrantFiled: July 30, 2019Date of Patent: June 1, 2021Assignee: MENTOR GRAPHICS CORPORATIONInventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Patent number: 10539615Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.Type: GrantFiled: February 27, 2018Date of Patent: January 21, 2020Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Publication number: 20190353705Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Patent number: 10437700Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.Type: GrantFiled: August 19, 2016Date of Patent: October 8, 2019Assignee: UltraSoC Technologies LimitedInventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
-
Patent number: 10296476Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.Type: GrantFiled: August 12, 2016Date of Patent: May 21, 2019Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
-
Patent number: 10088523Abstract: An integrated circuit chip comprising system circuitry and debugging circuitry. The system circuitry comprises a peripheral circuit. The debugging circuitry comprises a debug unit and a debug adapter. The debug unit is connected to the peripheral circuit. The debug adapter interfaces between the debug unit and a debug controller. The debug adapter is configured to receive a sequence of debug commands from the debug controller, each debug command instructing the debug unit to perform an action other than responding to a poll. In respect of each debug command, the debug adapter sends the debug command to the debug unit, and polls the debug unit to query whether the debug unit has performed the action instructed in that debug command.Type: GrantFiled: August 12, 2016Date of Patent: October 2, 2018Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Publication number: 20180188323Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Patent number: 9970985Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.Type: GrantFiled: August 12, 2016Date of Patent: May 15, 2018Assignee: UltraSoC Technologies LimitedInventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Patent number: 9632138Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: GrantFiled: October 9, 2015Date of Patent: April 25, 2017Assignee: ULTRASOC TECHNOLOGIES LIMITEDInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
-
Publication number: 20170052868Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.Type: ApplicationFiled: August 19, 2016Publication date: February 23, 2017Inventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer
-
Publication number: 20170046288Abstract: A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.Type: ApplicationFiled: August 12, 2016Publication date: February 16, 2017Inventors: Andrew Brian Thomas Hopkins, Michael Jonathan Thyer, Iain Craig Robertson
-
Publication number: 20170045583Abstract: An integrated circuit chip comprising system circuitry and debugging circuitry. The system circuitry comprises a peripheral circuit. The debugging circuitry comprises a debug unit and a debug adapter. The debug unit is connected to the peripheral circuit. The debug adapter interfaces between the debug unit and a debug controller. The debug adapter is configured to receive a sequence of debug commands from the debug controller, each debug command instructing the debug unit to perform an action other than responding to a poll. In respect of each debug command, the debug adapter sends the debug command to the debug unit, and polls the debug unit to query whether the debug unit has performed the action instructed in that debug command.Type: ApplicationFiled: August 12, 2016Publication date: February 16, 2017Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Publication number: 20170045584Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.Type: ApplicationFiled: August 12, 2016Publication date: February 16, 2017Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
-
Publication number: 20160033575Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: ApplicationFiled: October 9, 2015Publication date: February 4, 2016Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
-
Patent number: 9188638Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: GrantFiled: April 11, 2014Date of Patent: November 17, 2015Assignee: UltraSoC Technologies Ltd.Inventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer
-
Publication number: 20150226801Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.Type: ApplicationFiled: April 11, 2014Publication date: August 13, 2015Applicant: UltraSoC Technologies LtdInventors: Andrew Brian Thomas Hopkins, Iain Craig Robertson, Michael Jonathan Thyer