Abstract: The invention relates to a time-triggered computer system 800 that involves [i] a Processor (801) that has been designed to run in one of two or more pre-determined system modes, in each of which it will execute one or more tasks according to a predetermined task schedule; and [ii] a System-Mode Data Store (802) that contains information about the next system mode that the system is required to operate in; and [iii] a Processor Reset Mechanism (803) that will reset the Processor when it is necessary to change the system mode; and [iv] a Processor Configuration Mechanism (804) that is designed to configure the Processor in accordance with the required system mode after a Processor reset, using information stored in the System-Mode Data Store, and [v] a Task-Timing Data Store (805), that contains information about the Task WCET Limit and/or Task BCET Limit for one or more tasks that are executed by the Processor, and [vi] a Task-Execution-Time Monitoring Mechanism (806) that is designed to monitor the execution

Abstract: The invention relates to a time-triggered computer system (800) that involves [i] a Main Processor (801) that has been designed to run one or more tasks according to one or more predetermined task schedules, only one of which, the “active task schedule”, will be active at any point in time; [ii] a Monitor Processor (802) that has been designed to determine whether the Main Processor (801) is about to execute a task that is not in accordance with the active task schedule; [iii] a Communication Link (803) for passing information about future task executions between the Main Processor (801) and the Monitor Processor (802); and [iv] a Control Mechanism (comprising a System Control output (805), and/or a Communication Link B (806), and/or a Reset Link (807)) by means of which the Monitor Processor can halt or reset the Main Processor and take other corrective actions involving devices to which the computer system is connected, if the Monitor Processor determines that the Main Processor is about to execute a task t

Abstract: The invention relates to a time-triggered computer system 800 that involves [i] a Processor (801) that has been designed to run in one of two or more pre-determined system modes, in each of which it will execute one or more tasks according to a predetermined task schedule; and [ii] a System-Mode Data Store (802) that contains information about the next system mode that the system is required to operate in; and [iii] a Processor Reset Mechanism (803) that will reset the Processor when it is necessary to change the system mode; and [iv] a Processor Configuration Mechanism (804) that is designed to configure the Processor in accordance with the required system mode after a Processor reset, using information stored in the System-Mode Data Store, and [v] a Task-Timing Data Store (805), that contains information about the Task WCET Limit and/or Task BCET Limit for one or more tasks that are executed by the Processor, and [vi] a Task-Execution-Time Monitoring Mechanism (806) that is designed to monitor the execution

Abstract: The invention relates to a monitoring device for a processor comprising a means for monitoring the power consumption of the processor and a means for analysing the power consumption to detect abnormal operation of the processor.

Abstract: A debugging tool for a time-triggered system comprises means for interrogating the system code to determine task details; means for modifying the system code to include breakpoints, the position of the breakpoints being determined by the task details; means for executing the modified system code; means for measuring the time between pre-determined ones of said breakpoints; and means for reporting the timing results to a user.

Abstract: A tick source device (10) configured to accept a plurality of input signals and then to select one of said plurality of input signals and to use said one of said plurality of input signals as a source to generate a single output signal (12) to drive a processing device. A method of generating a signal to drive a processing device in accordance with the above is also disclosed.

Abstract: The invention relates to a monitoring device for a processor comprising a means for monitoring the power consumption of the processor and a means for analysing the power consumption to detect abnormal operation of the processor.

Abstract: A distributed system comprises a master node, at least one slave node, and two or more communication channels linking the master node to the at least one slave node. The master node is configured for transmitting the same message to the at least one slave node over each of the two or more communication channels, with a pre-determined delay between each channel transmission. In some embodiments, the system may also include a clock synchronization means configured such that the operation of each slave node is synchronized with the master node and/or a different slave node, irrespective of which channel transmission the slave node receives.