Patents by Inventor Michael Joseph Raneri

Michael Joseph Raneri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Timing functions to optimize code-execution time
    Patent number: 7890288
    Abstract: A method and system for optimizing a test plan of an Integrated Circuit (IC). The test plan includes two or more test sequences. A test sequence includes the measurement of a parameter of the IC. The total test time of the IC is reduced by performing one or more activities during a desired wait time associated with the measurement of the parameter. The test plan may be further optimized by modifying the one or more activities performed during the desired wait time.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: February 15, 2011
    Assignee: Anadigics, Inc.
    Inventor: Michael Joseph Raneri