Abstract: A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.

Abstract: A method includes automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage of the battery exceeds a recovery trip voltage or exceeds a shutdown trip voltage but is less than the recovery trip voltage and opened whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein. The method also includes rendering a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of a discharge switch following the charging of the capacitor.

Abstract: A method includes configuring a battery and a voltage regulator configured to regulate an output voltage of the battery to supply power to a memory of an electronic circuit also comprising non-memory circuitry. The method also includes switching the supply of power between the battery and the voltage regulator such that: the memory is powered from the battery when the non-memory circuitry is inactive, the memory is powered from a combination of voltage from the battery and the voltage regulator when the memory is about to communicate with the non-memory circuitry during a transition of the non-memory circuitry into an active state thereof, and the memory and the non-memory circuitry are powered from the voltage regulator during the active state of the non-memory circuitry. Thus, minimal current is drawn from the battery while a state of the memory of the electronic circuit is preserved.

Abstract: A method includes configuring a battery and a voltage regulator configured to regulate an output voltage of the battery to supply power to a memory of an electronic circuit also comprising non-memory circuitry. The method also includes switching the supply of power between the battery and the voltage regulator such that: the memory is powered from the battery when the non-memory circuitry is inactive, the memory is powered from a combination of voltage from the battery and the voltage regulator when the memory is about to communicate with the non-memory circuitry during a transition of the non-memory circuitry into an active state thereof, and the memory and the non-memory circuitry are powered from the voltage regulator during the active state of the non-memory circuitry. Thus, minimal current is drawn from the battery while a state of the memory of the electronic circuit is preserved.

Abstract: A method includes automatically charging a capacitor coupled to a battery configured to power a memory through a charge switch that is closed whenever a voltage of the battery exceeds a recovery trip voltage or exceeds a shutdown trip voltage but is less than the recovery trip voltage and opened whenever the voltage of the battery drops below the shutdown trip voltage such that a minimum voltage of the shutdown trip voltage is maintained on the battery, thereby enabling the memory to retain information therein. The method also includes rendering a stored energy of the capacitor available to all circuitry coupled to the battery following the charging thereof through coupling the capacitor in parallel with the battery based on closure of a discharge switch following the charging of the capacitor.

Abstract: A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.

Abstract: A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.

Abstract: A method includes forming a power control circuit through coupling a gate switch array between a buffer stage at an input of the power control circuit and an amplifier array including N amplifier stages in parallel to each other, with N>1. The method also includes coupling each of the N amplifier stages to a corresponding gate switch of the gate switch array, and controlling an output power of the power control circuit by switching one or more appropriate gate switches of the gate switch array to apply an input signal from the buffer stage to a corresponding one or more amplifier stages coupled to the one or more appropriate gate switches such that a maximum output power is achieved when all of the N amplifier stages are turned on and a minimum output power is achieved when only one amplifier stage is turned on.

Abstract: The present invention provides for a method and apparatus for increasing the linearity of the phase and gain of an amplifier circuit (10, 22). The amplifier circuit (10, 22) maintains linearity of the amplified output signal by monitoring the power levels of the input signal, and adjusting the supply voltage level(s) of the amplifier (18), based upon the measured input power levels. By appropriately adjusting the supply voltage level(s) of the amplifier (18) an output signal having a consistent gain and phase can be realized. Preferably a delay circuit (26) will be used to delay receipt of the input signal by the amplifier (18), so as to synchronize receipt of the input signal with the corresponding source voltage adjustments. The value of the delay preferably corresponds to the time for the envelope detector (14) to measure the instantaneous input power levels and the time for the processing unit (16) to determine and apply the appropriate supply voltage level(s) to the amplifier (18).