Patents by Inventor Michael Julian Daneman
Michael Julian Daneman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230286798Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: ApplicationFiled: March 3, 2023Publication date: September 14, 2023Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Patent number: 11731869Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.Type: GrantFiled: December 24, 2021Date of Patent: August 22, 2023Assignee: SiTime CorporationInventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
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Patent number: 11718518Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.Type: GrantFiled: September 9, 2020Date of Patent: August 8, 2023Assignee: SiTime CorporationInventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
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Patent number: 11618675Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: GrantFiled: December 6, 2021Date of Patent: April 4, 2023Assignee: SiTime CorporationInventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Publication number: 20220162063Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: ApplicationFiled: December 6, 2021Publication date: May 26, 2022Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Patent number: 11312622Abstract: A semiconductor device includes first and second exposed electrical contacts and a cavity having a microelectromechanical system (MEMS) structure therein. A conductive path extends from the first exposed electrical contact to the cavity and an over-voltage protection element electrically is coupled between the first and second exposed electrical contacts.Type: GrantFiled: June 29, 2020Date of Patent: April 26, 2022Assignee: SiTime CorporationInventors: Nicholas Miller, Ginel C. Hill, Charles I. Grosjean, Michael Julian Daneman, Paul M. Hagelin, Aaron Partridge
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Patent number: 11220425Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: GrantFiled: May 21, 2020Date of Patent: January 11, 2022Assignee: SiTime CorporationInventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Publication number: 20200391997Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: ApplicationFiled: May 21, 2020Publication date: December 17, 2020Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Publication number: 20200355824Abstract: In a method of operating a two-dimensional array of ultrasonic transducers, a plurality of array positions comprising pluralities of ultrasonic transducers of the two-dimensional array of ultrasonic transducers is defined, the plurality of array positions each comprising a portion of ultrasonic transducers of the two dimensional array of ultrasonic transducers. For each array position of the plurality of array positions, a plurality of ultrasonic transducers associated with the respective array position are activated. The activation includes transmitting ultrasonic signals from a first group of ultrasonic transducers of the plurality of ultrasonic transducers, wherein at least some ultrasonic transducers of the first group of ultrasonic transducers are phase delayed with respect to other ultrasonic transducers of the first group of ultrasonic transducers, the first group of ultrasonic transducers for forming a focused ultrasonic beam.Type: ApplicationFiled: June 1, 2020Publication date: November 12, 2020Applicant: InvenSense, Inc.Inventors: Nikhil APTE, Julius Ming-Lin TSAI, Michael Julian DANEMAN, Renata Melamud BERGER
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Patent number: 10800650Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.Type: GrantFiled: February 2, 2018Date of Patent: October 13, 2020Assignee: SiTime CorporationInventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
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Patent number: 10737934Abstract: A semiconductor device includes first and second exposed electrical contacts and a cavity having a microelectromechanical system (MEMS) structure therein. A conductive path extends from the first exposed electrical contact to the cavity and an over-voltage protection element electrically is coupled between the first and second exposed electrical contacts.Type: GrantFiled: March 2, 2018Date of Patent: August 11, 2020Assignee: SiTime CorporationInventors: Nicholas Miller, Ginel C. Hill, Charles I. Grosjean, Michael Julian Daneman, Paul M. Hagelin, Aaron Partridge
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Patent number: 10696547Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: GrantFiled: February 14, 2018Date of Patent: June 30, 2020Assignee: SiTime CorporationInventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Patent number: 10670716Abstract: In a method of operating a two-dimensional array of ultrasonic transducers, a plurality of array positions comprising pluralities of ultrasonic transducers of the two-dimensional array of ultrasonic transducers is defined, the plurality of array positions each comprising a portion of ultrasonic transducers of the two dimensional array of ultrasonic transducers. For each array position of the plurality of array positions, a plurality of ultrasonic transducers associated with the respective array position are activated. The activation includes transmitting ultrasonic signals from a first group of ultrasonic transducers of the plurality of ultrasonic transducers, wherein at least some ultrasonic transducers of the first group of ultrasonic transducers are phase delayed with respect to other ultrasonic transducers of the first group of ultrasonic transducers, the first group of ultrasonic transducers for forming a focused ultrasonic beam.Type: GrantFiled: September 15, 2016Date of Patent: June 2, 2020Assignee: InvenSense, Inc.Inventors: Nikhil Apte, Julius Ming-Lin Tsai, Michael Julian Daneman, Renata Melamud Berger
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Publication number: 20180257929Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.Type: ApplicationFiled: February 14, 2018Publication date: September 13, 2018Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
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Patent number: 9828240Abstract: A MEMS device includes a MEMS substrate with a movable element. Further included is a CMOS substrate with a cavity, the MEMS substrate disposed on top of the CMOS substrate. Additionally, a back cavity is connected to the CMOS substrate, the back cavity being formed at least partially by the cavity in the CMOS substrate and the movable element being acoustically coupled to the back cavity.Type: GrantFiled: February 18, 2016Date of Patent: November 28, 2017Assignee: INVENSENSE, INC.Inventors: Fang Liu, Michael Julian Daneman, Brian Kim, Anthony Minervini
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Publication number: 20170322305Abstract: In a method of operating a two-dimensional array of ultrasonic transducers, a plurality of array positions comprising pluralities of ultrasonic transducers of the two-dimensional array of ultrasonic transducers is defined, the plurality of array positions each comprising a portion of ultrasonic transducers of the two dimensional array of ultrasonic transducers. For each array position of the plurality of array positions, a plurality of ultrasonic transducers associated with the respective array position are activated. The activation includes transmitting ultrasonic signals from a first group of ultrasonic transducers of the plurality of ultrasonic transducers, wherein at least some ultrasonic transducers of the first group of ultrasonic transducers are phase delayed with respect to other ultrasonic transducers of the first group of ultrasonic transducers, the first group of ultrasonic transducers for forming a focused ultrasonic beam.Type: ApplicationFiled: September 15, 2016Publication date: November 9, 2017Applicant: InvenSense, Inc.Inventors: Nikhil APTE, Julius Ming-Lin TSAI, Michael Julian DANEMAN, Renata Melamud BERGER
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Patent number: 9802815Abstract: A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.Type: GrantFiled: December 2, 2015Date of Patent: October 31, 2017Assignee: INVENSENSE, INC.Inventors: Michael Julian Daneman, Mei-Lin Chan, Martin Lim, Fariboz Assaderaghi, Erhan Polatkan Ata
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Patent number: 9617141Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.Type: GrantFiled: July 15, 2015Date of Patent: April 11, 2017Assignee: INVENSENSE, INC.Inventors: Michael Julian Daneman, Martin Lim, Xiang Li, Li-Wen Hung
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Patent number: 9428379Abstract: A MEMS device is disclosed. The MEMS device comprises a first plate with a first surface and a second surface; and an anchor attached to a first substrate. The MEMS device further includes a second plate with a third surface and a fourth surface attached to the first plate. A linkage connects the anchor to the first plate, wherein the first plate and second plate are displaced in the presence of an acoustic pressure differential between the first and second surfaces of the first plate. The first plate, second plate, linkage, and anchor are all contained in an enclosure formed by the first substrate and a second substrate, wherein one of the first and second substrates contains a through opening to expose the first surface of the first plate to the environment.Type: GrantFiled: February 6, 2014Date of Patent: August 30, 2016Assignee: INVENSENSE, INC.Inventors: Erhan Polatkan Ata, Martin Lim, Xiang Li, Stephen Lloyd, Michael Julian Daneman
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Publication number: 20160167956Abstract: A MEMS device includes a MEMS substrate with a movable element. Further included is a CMOS substrate with a cavity, the MEMS substrate disposed on top of the CMOS substrate. Additionally, a back cavity is connected to the CMOS substrate, the back cavity being formed at least partially by the cavity in the CMOS substrate and the movable element being acoustically coupled to the back cavity.Type: ApplicationFiled: February 18, 2016Publication date: June 16, 2016Inventors: Fang Liu, Michael Julian Daneman, Brian Kim, Anthony Minervini