Patents by Inventor Michael Julian Daneman

Michael Julian Daneman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230286798
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 14, 2023
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 11731869
    Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: August 22, 2023
    Assignee: SiTime Corporation
    Inventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
  • Patent number: 11718518
    Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 8, 2023
    Assignee: SiTime Corporation
    Inventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
  • Patent number: 11618675
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: April 4, 2023
    Assignee: SiTime Corporation
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Publication number: 20220162063
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Application
    Filed: December 6, 2021
    Publication date: May 26, 2022
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 11312622
    Abstract: A semiconductor device includes first and second exposed electrical contacts and a cavity having a microelectromechanical system (MEMS) structure therein. A conductive path extends from the first exposed electrical contact to the cavity and an over-voltage protection element electrically is coupled between the first and second exposed electrical contacts.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: April 26, 2022
    Assignee: SiTime Corporation
    Inventors: Nicholas Miller, Ginel C. Hill, Charles I. Grosjean, Michael Julian Daneman, Paul M. Hagelin, Aaron Partridge
  • Patent number: 11220425
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: January 11, 2022
    Assignee: SiTime Corporation
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Publication number: 20200391997
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Application
    Filed: May 21, 2020
    Publication date: December 17, 2020
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Publication number: 20200355824
    Abstract: In a method of operating a two-dimensional array of ultrasonic transducers, a plurality of array positions comprising pluralities of ultrasonic transducers of the two-dimensional array of ultrasonic transducers is defined, the plurality of array positions each comprising a portion of ultrasonic transducers of the two dimensional array of ultrasonic transducers. For each array position of the plurality of array positions, a plurality of ultrasonic transducers associated with the respective array position are activated. The activation includes transmitting ultrasonic signals from a first group of ultrasonic transducers of the plurality of ultrasonic transducers, wherein at least some ultrasonic transducers of the first group of ultrasonic transducers are phase delayed with respect to other ultrasonic transducers of the first group of ultrasonic transducers, the first group of ultrasonic transducers for forming a focused ultrasonic beam.
    Type: Application
    Filed: June 1, 2020
    Publication date: November 12, 2020
    Applicant: InvenSense, Inc.
    Inventors: Nikhil APTE, Julius Ming-Lin TSAI, Michael Julian DANEMAN, Renata Melamud BERGER
  • Patent number: 10800650
    Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 13, 2020
    Assignee: SiTime Corporation
    Inventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
  • Patent number: 10737934
    Abstract: A semiconductor device includes first and second exposed electrical contacts and a cavity having a microelectromechanical system (MEMS) structure therein. A conductive path extends from the first exposed electrical contact to the cavity and an over-voltage protection element electrically is coupled between the first and second exposed electrical contacts.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 11, 2020
    Assignee: SiTime Corporation
    Inventors: Nicholas Miller, Ginel C. Hill, Charles I. Grosjean, Michael Julian Daneman, Paul M. Hagelin, Aaron Partridge
  • Patent number: 10696547
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 30, 2020
    Assignee: SiTime Corporation
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 10670716
    Abstract: In a method of operating a two-dimensional array of ultrasonic transducers, a plurality of array positions comprising pluralities of ultrasonic transducers of the two-dimensional array of ultrasonic transducers is defined, the plurality of array positions each comprising a portion of ultrasonic transducers of the two dimensional array of ultrasonic transducers. For each array position of the plurality of array positions, a plurality of ultrasonic transducers associated with the respective array position are activated. The activation includes transmitting ultrasonic signals from a first group of ultrasonic transducers of the plurality of ultrasonic transducers, wherein at least some ultrasonic transducers of the first group of ultrasonic transducers are phase delayed with respect to other ultrasonic transducers of the first group of ultrasonic transducers, the first group of ultrasonic transducers for forming a focused ultrasonic beam.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: June 2, 2020
    Assignee: InvenSense, Inc.
    Inventors: Nikhil Apte, Julius Ming-Lin Tsai, Michael Julian Daneman, Renata Melamud Berger
  • Publication number: 20180257929
    Abstract: A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
    Type: Application
    Filed: February 14, 2018
    Publication date: September 13, 2018
    Inventors: Michael Julian Daneman, Charles I. Grosjean, Paul M. Hagelin
  • Patent number: 9828240
    Abstract: A MEMS device includes a MEMS substrate with a movable element. Further included is a CMOS substrate with a cavity, the MEMS substrate disposed on top of the CMOS substrate. Additionally, a back cavity is connected to the CMOS substrate, the back cavity being formed at least partially by the cavity in the CMOS substrate and the movable element being acoustically coupled to the back cavity.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 28, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Fang Liu, Michael Julian Daneman, Brian Kim, Anthony Minervini
  • Publication number: 20170322305
    Abstract: In a method of operating a two-dimensional array of ultrasonic transducers, a plurality of array positions comprising pluralities of ultrasonic transducers of the two-dimensional array of ultrasonic transducers is defined, the plurality of array positions each comprising a portion of ultrasonic transducers of the two dimensional array of ultrasonic transducers. For each array position of the plurality of array positions, a plurality of ultrasonic transducers associated with the respective array position are activated. The activation includes transmitting ultrasonic signals from a first group of ultrasonic transducers of the plurality of ultrasonic transducers, wherein at least some ultrasonic transducers of the first group of ultrasonic transducers are phase delayed with respect to other ultrasonic transducers of the first group of ultrasonic transducers, the first group of ultrasonic transducers for forming a focused ultrasonic beam.
    Type: Application
    Filed: September 15, 2016
    Publication date: November 9, 2017
    Applicant: InvenSense, Inc.
    Inventors: Nikhil APTE, Julius Ming-Lin TSAI, Michael Julian DANEMAN, Renata Melamud BERGER
  • Patent number: 9802815
    Abstract: A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: October 31, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Michael Julian Daneman, Mei-Lin Chan, Martin Lim, Fariboz Assaderaghi, Erhan Polatkan Ata
  • Patent number: 9617141
    Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: April 11, 2017
    Assignee: INVENSENSE, INC.
    Inventors: Michael Julian Daneman, Martin Lim, Xiang Li, Li-Wen Hung
  • Patent number: 9428379
    Abstract: A MEMS device is disclosed. The MEMS device comprises a first plate with a first surface and a second surface; and an anchor attached to a first substrate. The MEMS device further includes a second plate with a third surface and a fourth surface attached to the first plate. A linkage connects the anchor to the first plate, wherein the first plate and second plate are displaced in the presence of an acoustic pressure differential between the first and second surfaces of the first plate. The first plate, second plate, linkage, and anchor are all contained in an enclosure formed by the first substrate and a second substrate, wherein one of the first and second substrates contains a through opening to expose the first surface of the first plate to the environment.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 30, 2016
    Assignee: INVENSENSE, INC.
    Inventors: Erhan Polatkan Ata, Martin Lim, Xiang Li, Stephen Lloyd, Michael Julian Daneman
  • Publication number: 20160167956
    Abstract: A MEMS device includes a MEMS substrate with a movable element. Further included is a CMOS substrate with a cavity, the MEMS substrate disposed on top of the CMOS substrate. Additionally, a back cavity is connected to the CMOS substrate, the back cavity being formed at least partially by the cavity in the CMOS substrate and the movable element being acoustically coupled to the back cavity.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 16, 2016
    Inventors: Fang Liu, Michael Julian Daneman, Brian Kim, Anthony Minervini