Abstract: A single ASIC memory controller has full interconnectivity between various modes on the ASIC: input controller, memory controller, and output controller. The single ASIC includes an input controller section, a memory controller section, and an output controller section. The ASIC architecture is designed to allow any of the sections to be bypassed. Using the bypass mechanism, the ASIC can be combined with other like ASICs to increase system performance and capabilities without the need for ASIC redesign. The ASIC design can be used in memory subsystems that are scalable depending on user requirements.

Abstract: A method and a switching system for connecting multiple requestors to multiple memory units simultaneously. This is accomplished by a switching system that employs multiplexing logic, control logic, multiple data input and output ports and a unique system interconnection topology. Independent data input ports comprised of multiplexing logic controlled by a control logic, simultaneously channel multiple fetch and store commands from the requestors to the memory units. Similarly, independent data output ports comprised of a second multiplexing logic controlled by a second control logic, simultaneously channels multiple return signals from the memory units to the requestors. The switching system of the present invention incorporates the unique system interconnection topology concept of feed-through boards and modular backplane boards.

Abstract: Modular expansion of a backplane is achieved by means of a modular backplane circuit board that plugs into the backplane side of a backplane parallel to that backplane. The backplane board provides a parallel backplane path between boards on the computer system. When unit boards are added to the foreplane side which require additional electrical paths for connection purposes, a modular backplane board may be added to the backplane side of the backplane to provide such path. In the preferred embodiment a gate array is added to the backplane board to provide management functions in handling the electrical connections on the backplane board.

Abstract: Disclosed is an apparatus and method for verifying the authenticity of a circuit board incorporated in a system. The method employs signal representing a unique identifier, such as a serial number and an associated error check code, to identify the circuit board. The identifier signal is passed from the circuit board to the system when the circuit board is initialized. To verify that a circuit board is authentic, the error check code (ECC) represented in the second part of the circuit board's identifier signal is verified. If the ECC is not correct then the circuit board is left unused. Next, the first part of the identifier signal (e.g. the serial number) is compared to the identifier signals for all other circuit boards mounted within the system. If a match of any two identifier signals is found, all circuit boards associated with the common identifier signal are left unused. If no duplicates are found and the ECC was correct, the circuit board is permitted to function.

Abstract: A memory system provides a method for error detection and correction. Large data words are divided into multiple error correction zones. One zone from each of two or more words are combined to form an error domain. Address bits are also included in the domains. Check bits are generated from the data bits in each domain and stored with the data. During data retrieval, each domain is processed separately, generating a syndrome for each domain. The syndromes provide indication of bit errors, allowing the correction of a single-bit error in each domain. Multiple-bit errors may thus be corrected within each word using a single-bit error correction code. Data are distributed in physical memory so that, within each domain, no more than one data bit is stored in the same memory device. This method provides full error correction capability in the presence of a catastrophic memory package failure, so long as failures in multiple packages do not cause multiple errors within a single error correction domain.

Abstract: The present disclosure describes electronic circuits for detecting functional failures of random access memory (RAM) devices. The circuits generate a bit pattern sequence for each memory address location and write the pattern into the memory. Subsequently, the pattern is regenerated and compared for equality with the pattern read from the memory. A complete RAM test comprises a sequence of patterns where each pattern is made to fill the entire memory matrix once. The number of test sequence patterns is a function of the bit organization of the RAM under test. Assuming that the device under test is a RAM of the type included within the tester's repertoire of testable memory devices, failure to achieve equality of the write/read patterns is indicative of a defective RAM.