Abstract: A non-volatile (NV) memory may store hiberfile data before entering a hibernate state, and retrieve the data upon resume from hibernation. The reserve space in the NV memory (i.e., the erased blocks available to be used while in the run-time mode) may be used to store hiberfile data. Further, a write-through cache policy may be used to assure that all of the hiberfile data saved in cache will also be stored on the disk drive during the hibernation, so that if the cache and the disk drive are separated during hibernation, the full correct hiberfile data will still be available for a resume operation.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: Method and apparatus to improve cache performance using interarrival times between demand requests are described.

Abstract: Various embodiments of the invention use a non-volatile (NV) memory to store hiberfile data before entering a hibernate state, and retrieve the data upon resume from hibernation. Unlike conventional systems, the reserve space in the NV memory (i.e., the erased blocks available to be used while in the run-time mode) may be used to store hiberfile data. Further, a write-through cache policy may be used to assure that all of the hiberfile data saved in cache will also be stored on the disk drive during the hibernation, so that if the cache and the disk drive are separated during hibernation, the full correct hiberfile data will still be available for a resume operation.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.

Abstract: The invention includes a platform having a controller coupled to a central processing unit through a system bus. The platform also includes a register device coupled between the central processing unit and the controller. Moreover, the platform also includes a bus coupled to the controller having an end that is adapted to receive a device. The register device includes a depth that is adapted to hold all instruction packets from the central processing unit without presenting delays due to full conditions.

Abstract: The invention includes a platform having a controller coupled to a central processing unit through a system bus. The platform also includes a register device coupled between the central processing unit and the controller. Moreover, the platform also includes a bus coupled to the controller having an end that is adapted to receive a device. The register device includes a depth that is adapted to hold all instruction packets from the central processing unit without presenting delays due to full conditions.

Abstract: The invention includes a platform having a controller coupled to a central processing unit through a system bus. The platform also includes a register device coupled between the central processing unit and the controller. Moreover, the platform also includes a bus coupled to the controller having an end that is adapted to receive a device. The register device includes a depth that is adapted to hold all instruction packets from the central processing unit without presenting delays due to full conditions.