Patents by Inventor Michael K. Fertig
Michael K. Fertig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9697146Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.Type: GrantFiled: December 27, 2012Date of Patent: July 4, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Douglas R. Williams, Vydhyanathan Kalyanasundharam, Marius Evers, Michael K. Fertig
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Patent number: 8954635Abstract: A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.Type: GrantFiled: August 31, 2011Date of Patent: February 10, 2015Assignee: Advanced Micro Devices, Inc.Inventors: William Hughes, Chengping Yang, Michael K. Fertig
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Patent number: 8787368Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.Type: GrantFiled: December 7, 2010Date of Patent: July 22, 2014Assignee: Advanced Micro Devices, Inc.Inventors: William A. Hughes, Chenping Yang, Michael K. Fertig
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Publication number: 20140189700Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Douglas R. Williams, Vydhyanathan Kalyanasundharam, Marius Evers, Michael K. Fertig
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Publication number: 20130054864Abstract: A device includes a link interface circuit, a first plurality of allocated buffers, and a second plurality of non-allocated buffers. The link interface circuit is operable to communicate over a communications link using a plurality of virtual channels. A different subset of the plurality of allocated buffers is allocated to each of the virtual channels. The non-allocated buffers are not allocated to a particular virtual channel. The link interface circuit is operable to receive a first transaction over the communications link and assign the first transaction to one of the allocated buffers or one of the non-allocated buffers.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Inventors: William Hughes, Chengping Yang, Michael K. Fertig
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Publication number: 20120155273Abstract: A multi-chip module configuration includes two processors, each having two nodes, each node including multiple cores or compute units. Each node is connected to the other nodes by links that are high bandwidth or low bandwidth. Routing of traffic between the nodes is controlled at each node according to a routing table and/or a control register that optimize bandwidth usage and traffic congestion control.Type: ApplicationFiled: December 15, 2010Publication date: June 21, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: William A. Hughes, Chenping Yang, Michael K. Fertig, Kevin M. Lepak
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Publication number: 20120140768Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.Type: ApplicationFiled: December 7, 2010Publication date: June 7, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: William A. Hughes, Chenping Yang, Michael K. Fertig
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Patent number: 7930485Abstract: A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.Type: GrantFiled: July 19, 2007Date of Patent: April 19, 2011Assignee: Globalfoundries Inc.Inventors: Michael K Fertig, Patrick Conway, Kevin Michael Lepak, Cissy Xumin Yuan
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Patent number: 7881303Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.Type: GrantFiled: December 13, 2006Date of Patent: February 1, 2011Assignee: GLOBALFOUNDRIES, Inc.Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig
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Patent number: 7840873Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.Type: GrantFiled: December 13, 2006Date of Patent: November 23, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig
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Publication number: 20090024835Abstract: A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.Type: ApplicationFiled: July 19, 2007Publication date: January 22, 2009Inventors: Michael K. Fertig, Patrick Conway, Kevin Michael Lepak, Cissy Xumin Yuan
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Publication number: 20080148131Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig
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Publication number: 20080148135Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig
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Patent number: RE44487Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.Type: GrantFiled: September 22, 2011Date of Patent: September 10, 2013Assignee: GLOBALFOUNDRIES Inc.Inventors: William A. Hughes, Chen-Ping Yang, Greggory D. Donley, Michael K. Fertig