Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

Abstract: Technology is disclosed for a memory system having a cross-point array with threshold switching selector memory cells. Each memory cell has a two-terminal threshold switching selector memory element that may be programmed to two different on-state conductances in order to store information. One bit value may be represented by a high-resistance state (HRS) when in the on-state and another bit value may be represented by a low-resistance state (LRS) when in the on-state. In one aspect, a conditioning signal is applied to the memory cell prior to programming. Applying a program signal with the opposite polarity as the conditioning signal may result in a higher conductance in the on-state than applying a program signal with the same polarity as the conditioning signal. The memory element may also serve as a selector for the memory cell. The memory element may include an Ovonic Threshold Switch (OTS).

Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.

Abstract: A method is provided that includes reading a plurality of resistance-switching memory cells comprising a block of data, decoding the block of data using an error correction code decoder, and based on results of the decoding, selectively performing an overwrite-read process to read the block of data. The overwrite read process determines a change in resistance of the resistance-switching memory cells in response to a write pulse.

Abstract: An apparatus is provided that includes a plurality of data arrays each comprising first memory cells, a plurality of read reference arrays each comprising second memory cells, a plurality of write reference arrays each comprising third memory cells, an access block comprising a memory cell from each of the plurality of data arrays, each of the plurality of read reference arrays, and each of the plurality of write reference arrays, and a memory controller. The memory controller is configured to determine a read threshold voltage to compensate a drift of a threshold voltage of the first memory cells, wherein the read threshold voltage is determined based on threshold voltages of a plurality of second memory cells, and a read offset voltage to compensate an offset voltage of the first memory cells, wherein the read offset voltage is determined based on offset voltages of a plurality of second memory cells.

Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.

Abstract: A memory system is provided that includes a first memory array including a first memory cell, a second memory array including a second memory cell, and a memory controller configured to determine a threshold voltage of the second memory cell to compensate a drift of a threshold voltage of the first memory cell and/or determine an offset voltage of the second memory cell to compensate an offset voltage of the first memory cell.

Abstract: A method is provided that includes applying a read voltage to a resistance-switching memory cell to determine a first memory cell resistance, applying a first write voltage to the resistance-switching memory cell, applying the read voltage to the resistance-switching memory cell to determine a second memory cell resistance, and comparing the first memory cell resistance to the second memory cell resistance to determine that the resistance-switching memory cell is in a first memory state or a second memory state.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element. The first selector element includes a first snapback current, and the second selector element includes a second snapback current lower than the first snapback current.

Abstract: An apparatus is provided that includes a bit line above a substrate, a word line above the substrate, and a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. The isolation element includes a first selector element coupled in series with a second selector element.

Abstract: A patterned magnetic media having offset servo and data regions. The media can be constructed by a method that allows both a data region and a servo region to be patterned without the patterning of one region adversely affecting the patterning of the other region. The method results in a patterned data region a patterned servo region and intermediate regions between the servo and data regions. The intermediate regions, which are most likely, but not necessarily, asymmetrical with one another indicate that the method has been used to pattern the media.

Abstract: In one general embodiment, an apparatus includes a write pole, a near field transducer, a waveguide for delivering light to the near field transducer, and a first heating device positioned between the write pole and at least one of the waveguide and the near field transducer.

Abstract: A method of storing data in a storage medium includes determining a compensation unit for a portion of the storage medium, reading a first set of bit values from the portion of the storage medium, determining a compensation value based at least in part on an erroneous bit value of the first set of bit values and the compensation unit, and storing the compensation value in association with the portion of the storage medium.

Abstract: According to one embodiment, a patterned magnetic storage medium is disclosed herein. The magnetic storage medium includes a pattern formed on a substrate. The pattern includes at least a first and second feature and an edge defined between the first and second features. Additionally, the magnetic storage medium includes a magnetic layer formed on the pattern. The magnetic layer includes grains separated by a non-magnetic segregant boundary. The segregant boundary is positioned above the edge of the pattern.