Patents by Inventor Michael K. Harper
Michael K. Harper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11594637Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.Type: GrantFiled: March 27, 2020Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Leonard P. Guler, Stephen Snyder, Biswajeet Guha, William Hsu, Urusa Alaan, Tahir Ghani, Michael K. Harper, Vivek Thirtha, Shu Zhou, Nitesh Kumar
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Patent number: 11569231Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.Type: GrantFiled: March 15, 2019Date of Patent: January 31, 2023Assignee: Intel CorporationInventors: Stephen D Snyder, Leonard Guler, Richard Schenker, Michael K Harper, Sam Sivakumar, Urusa Alaan, Stephanie A Bojarski, Achala Bhuwalka
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Publication number: 20220093589Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Inventors: Leonard P. GULER, William HSU, Biswajeet GUHA, Martin WEISS, Apratim DHAR, William T. BLANTON, John H. IRBY, IV, James F. BONDI, Michael K. HARPER, Charles H. WALLACE, Tahir GHANI, Benedict A. SAMUEL, Stefan DICKERT
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Publication number: 20220093592Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Leonard P. GULER, Michael K. HARPER, William HSU, Biswajeet GUHA, Tahir GHANI, Niels ZUSSSBLATT, Jeffrey Miles TAN, Benjamin KRIEGEL, Mohit K. HARAN, Reken PATEL, Oleg GOLONZKA, Mohammad HASAN
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Publication number: 20210408257Abstract: Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Nicole THOMAS, Michael K. HARPER, Leonard P. GULER, Marko RADOSAVLJEVIC, Thoe MICHAELOS
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Publication number: 20210305430Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.Type: ApplicationFiled: March 27, 2020Publication date: September 30, 2021Inventors: Leonard P. GULER, Stephen SNYDER, Biswajeet GUHA, William HSU, Urusa ALAAN, Tahir GHANI, Michael K. HARPER, Vivek THIRTHA, Shu ZHOU, Nitesh KUMAR
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Publication number: 20200295002Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.Type: ApplicationFiled: March 15, 2019Publication date: September 17, 2020Applicant: Intel CorporationInventors: Stephen D. Snyder, Leonard Guler, Richard Schenker, Michael K. Harper, Sam Sivakumar, Urusa Alaan, Stephanie A. Bojarski, Achala Bhuwalka
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Patent number: 9905693Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.Type: GrantFiled: July 19, 2017Date of Patent: February 27, 2018Assignee: Intel CorporationInventors: Michael L. Hattendorf, Pragyansri Pathi, Michael K. Harper
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Publication number: 20170323965Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.Type: ApplicationFiled: July 19, 2017Publication date: November 9, 2017Inventors: Michael L. HATTENDORF, Pragyansri PATHI, Michael K. HARPER
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Patent number: 9768249Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.Type: GrantFiled: June 26, 2013Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Michael L. Hattendorf, Pragyansri Pathi, Michael K. Harper
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Publication number: 20160204193Abstract: Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems incorporating such integrated circuits, and methods for forming them are discussed.Type: ApplicationFiled: June 26, 2013Publication date: July 14, 2016Inventors: Michael L. HATTENDORF, Pragyansri PATHI, Michael K. HARPER
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Patent number: 8629039Abstract: A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.Type: GrantFiled: May 2, 2013Date of Patent: January 14, 2014Assignee: Intel CorporationInventors: Willy Rachmady, Justin S. Sandford, Michael K. Harper
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Publication number: 20130273710Abstract: A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.Type: ApplicationFiled: May 2, 2013Publication date: October 17, 2013Inventors: Willy Rachmady, Justin S. Sandford, Michael K. Harper
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Patent number: 8441074Abstract: A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas.Type: GrantFiled: July 15, 2010Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Willy Rachmady, Justin S. Sandford, Michael K. Harper
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Patent number: 8377771Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.Type: GrantFiled: May 23, 2012Date of Patent: February 19, 2013Assignee: Intel CorporationInventors: Willy Rachmady, Brian McIntrye, Michael K. Harper, Subhash M. Joshi
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Patent number: 8314034Abstract: Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.Type: GrantFiled: December 23, 2010Date of Patent: November 20, 2012Assignee: Intel CorporationInventors: Elliot N. Tan, Michael K. Harper
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Publication number: 20120264285Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.Type: ApplicationFiled: May 23, 2012Publication date: October 18, 2012Applicant: Intel CorporationInventors: Willy Rachmady, Brian Mclntyre, Michael K. Harper, Subhash M. Joshi
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Publication number: 20120164837Abstract: Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Elliot N. Tan, Michael K. Harper
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Patent number: 8193641Abstract: A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the spacers, a recessed workfunction metal conformally deposited on the high-k dielectric and along a portion of the spacer sidewalls, a second workfunction metal conformally deposited on the recessed workfunction metal, and an electrode metal deposited on the second workfunction metal. The transistor gate may be formed by conformally depositing the high-k dielectric into a trench between the spacers on the substrate, conformally depositing a workfunction metal atop the high-k dielectric, depositing a sacrificial mask atop the workfunction metal, etching a portion of the sacrificial mask to expose a portion of the workfunction metal, and etching the exposed portion of the workfunction metal to form the recessed workfunction metal. The second workfunction metal and the electrode metal may be deposited atop the recessed workfunction metal.Type: GrantFiled: May 9, 2006Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Willy Rachmady, Brian McIntyre, Michael K. Harper, Subhash M. Joshi
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Patent number: 7977248Abstract: In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.Type: GrantFiled: December 31, 2007Date of Patent: July 12, 2011Assignee: Intel CorporationInventors: Elliot Tan, Michael K. Harper, James Jeong