Abstract: Embodiments of an IC device are disclosed. In some embodiments, an integrated circuit (IC) device, includes: an first active semiconductor layer that includes first active semiconductor device regions; a second active semiconductor layer that includes active semiconductor regions, the second active semiconductor layer being connected to the first active semiconductor layer and being positioned over the first active semiconductor layer; a first redistribution layer positioned over the second active conductor layer, the first redistribution layer is electrically connected to the first active semiconductor layer and the second active semiconductor layer; a passivation layer positioned on the first redistribution layer; a second redistribution layer positioned over the passivation layer, wherein the second redistribution layer is electrically connected to the first redistribution layer.

Abstract: Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

Abstract: Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

Abstract: Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

Abstract: Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

Abstract: Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device.

Abstract: A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

Abstract: A method and circuit for implementing low duty cycle distortion and low power differential to single ended level shifter, and a design structure on which the subject circuit resides are provided. The circuit includes an input differential amplifier providing positive and negative differential amplifier output signals coupled to an output amplifier providing a single ended output signal. The output amplifier amplifies and inverts the negative differential amplifier output signal. The output amplifier amplifies and superimposes the positive differential amplifier output signal with the amplified and inverted negative differential amplifier output signal, providing the single ended output signal with low duty cycle distortion.

Abstract: A method and circuit for implementing low duty cycle distortion and low power differential to single ended level shifter, and a design structure on which the subject circuit resides are provided. The circuit includes an input differential amplifier providing positive and negative differential amplifier output signals coupled to an output amplifier providing a single ended output signal. The output amplifier amplifies and inverts the negative differential amplifier output signal. The output amplifier amplifies and superimposes the positive differential amplifier output signal with the amplified and inverted negative differential amplifier output signal, providing the single ended output signal with low duty cycle distortion.

Abstract: A method and circuit for implementing protection for complementary metal oxide semiconductor (CMOS) output drivers, and a design structure on which the subject circuit resides are provided. An output driver stage transistor stack includes a plurality of series connected PFETs series connected with a plurality of series connected NFETs connected between upper and lower voltage supply rails. A pair of offset DC voltage levels provides respective gate voltages of an intermediate PFET and an intermediate NFET in the output driver stage transistor stack. A pair of pre-driver circuits receiving voltage level translated logic signals drive respective gate inputs of the upper PFET and the lower NFET in the output driver stage transistor stack. A voltage feedback circuit provides respective gate voltages of the PFET and NFET connected together in the output driver stage transistor stack.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

Abstract: A method of locating a short circuit of a shorted circuit path in a circuit layout includes receiving a connecting stack of the circuit layout, receiving the circuit layout defining the connecting stack, receiving at least four virtual probe locations, identifying shortest paths between the at least four virtual probes, and outputting an intersection of the shortest paths, the intersection including the location of the short circuit. According to the method, the connecting stack includes interconnecting paths representing conductive traces of a circuit design, the at least four virtual probe locations exist on the interconnecting stack on at least two different nodes along the shorted circuit path, and the shortest paths are identified between pairs of the at least four probes and are between the at least two different nodes.

Abstract: A design structure embodied in a machine readable medium used in a design process includes high-speed interface between a first network component and a second network component, the interface including a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

Abstract: A high-speed interface between a first network component and a second network component includes a positive voltage input (VINP) and a negative voltage input (VINN) for receiving an input data signal from the first network component; the positive voltage input (VINP) coupled to a negative output circuit (OUTN) and the negative voltage input (VINN) by a positive input bus and a negative input bus, the negative voltage input (VINN) also coupled to a positive output circuit (OUTP). Implementing the high-speed interface calls for applying a bias to the a positive input bus and a negative input bus to periodically multiplex a data signal, thus providing a common receiving path for functional data and wrap data of the data signal.

Abstract: A voltage level shifting device for translating a lower operating voltage to a higher operating voltage includes a first input node coupled to a first pull down device and a second input node coupled to a second pull down device. The second node receives a complementary logic signal with respect to the first input node, the first and second input nodes associated with the lower operating voltage. A first pull up device is in series with the first pull down device and second pull up device is in series with the second pull down device, with the first and second pull up devices coupled to a power supply at the higher operating voltage. An output node is between the second pull down device and the second pull up device, the output node controlling the conductivity of the first pull up device. A clamping device is in parallel with the first pull up device, and configured to prevent the second pull up device from becoming fully saturated.

Abstract: A termination circuit for a differential transmission line. The termination circuit comprises a plurality of resistive sub circuits. Each of the resistive sub circuits comprises a PFET and an NFET in parallel. A first resistor is connected at one end to a drain of the NFET and a source of the PFET, and connected at an opposite end to one line of the differential transmission line. A second resistor is connected at one end to a source of the NFET and a drain of the PFET, and connected an opposite end to another line of the differential transmission line. Optionally, there is another resistor connected between the differential transmission line, whereby the termination resistance is based on this other resistance in parallel with one or more of the resistive sub circuits which are enabled. Means are provided to selectively enable one or more of the resistive sub circuits to yield a desired resistance to terminate the differential transmission line.

Abstract: A termination circuit for a differential transmission line. The termination circuit comprises a plurality of resistive sub circuits. Each of the resistive sub circuits comprises a PFET and an NFET in parallel. A first resistor is connected at one end to a drain of the NFET and a source of the PFET, and connected at an opposite end to one line of the differential transmission line. A second resistor is connected at one end to a source of the NFET and a drain of the PFET, and connected an opposite end to another line of the differential transmission line. Optionally, there is another resistor connected between the differential transmission line, whereby the termination resistance is based on this other resistance in parallel with one or more of the resistive sub circuits which are enabled. Means are provided to selectively enable one or more of the resistive sub circuits to yield a desired resistance to terminate the differential transmission line.