Patents by Inventor Michael K. Kroener
Michael K. Kroener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10671398Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.Type: GrantFiled: August 2, 2017Date of Patent: June 2, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
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Patent number: 10671399Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.Type: GrantFiled: October 27, 2017Date of Patent: June 2, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
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Patent number: 10572223Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: GrantFiled: March 12, 2019Date of Patent: February 25, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Publication number: 20190212983Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Patent number: 10331407Abstract: A method for performing tiny detection in floating-point operations with a floating-point unit. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.Type: GrantFiled: November 11, 2017Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
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Patent number: 10310815Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: GrantFiled: November 30, 2017Date of Patent: June 4, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Publication number: 20190163445Abstract: A method to produce a final product from a multiplicand and a multiplier is provided. The method is executed by a parallel decimal multiplication hardware architecture, which includes a 3× generator, at least one additional generator, a multiplier recoder, a partial product tree, and a decimal adder. The 3× generator, the at least one additional generator, and the multiplier recoder generate decimal partial products from the multiplicand and the multiplier. The partial product tree executes a reduction of the decimal partial products to produce two corresponding partial product accumulations. The decimal adder adds the two corresponding partial product accumulations of the decimal partial products to produce the final product.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Inventors: Steven R. Carlough, Michael Klein, Michael K. Kroener, Silvia M. Mueller
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Patent number: 10241756Abstract: A floating-point unit for performing tiny detection in floating-point operations. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.Type: GrantFiled: July 11, 2017Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
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Publication number: 20190042268Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.Type: ApplicationFiled: October 27, 2017Publication date: February 7, 2019Inventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
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Publication number: 20190042267Abstract: A computer processing system is provided. The computer processing system includes a processor configured to insert a move instruction in an instruction scheduling dependency graph generated for operands of the instruction operating on register pairs to ensure operand readiness for all of the operands used by the instruction operating on register pairs.Type: ApplicationFiled: August 2, 2017Publication date: February 7, 2019Inventors: Maarten J. Boersma, Sundeep Chadha, Kurt A. Feiste, Michael J. Genden, Michael K. Kroener, David R. Terry
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Publication number: 20190018651Abstract: A method for performing tiny detection in floating-point operations with a floating-point unit. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.Type: ApplicationFiled: November 11, 2017Publication date: January 17, 2019Inventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
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Publication number: 20190018650Abstract: A floating-point unit for performing tiny detection in floating-point operations. The floating-point unit is configured to implement a fused-multiply-add operation on three wide operands. The floating-point unit comprise: a multiplier, a left shifter, a right shifter a select circuit comprising a 3-to-2 compressor, an adder connected to the dataflow from the select circuit, a first feedback path connecting a carry output) of the adder to the select circuit, and a second feedback path connecting an output of the adder to the left and right shifters for passing an intermediate wide result through the left and right shifters. The adder is configured to provide an unrounded result for tiny detection.Type: ApplicationFiled: July 11, 2017Publication date: January 17, 2019Inventors: Michael K. Kroener, Silvia M. Mueller, Andreas Wagner
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Patent number: 10168993Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: GrantFiled: October 20, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Patent number: 10101967Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: GrantFiled: February 22, 2017Date of Patent: October 16, 2018Assignee: International Business Machines CorporationInventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Publication number: 20180239589Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: ApplicationFiled: October 20, 2017Publication date: August 23, 2018Inventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Publication number: 20180239588Abstract: A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.Type: ApplicationFiled: February 22, 2017Publication date: August 23, 2018Inventors: Michael K. Kroener, Silvia M. Mueller, Manuela Niekisch, Kerstin C. Schelm
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Patent number: 9128759Abstract: An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value.Type: GrantFiled: November 27, 2012Date of Patent: September 8, 2015Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Adam B. Collura, Michael K. Kroener, Silvia M. Mueller
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Patent number: 9128758Abstract: According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format.Type: GrantFiled: November 15, 2011Date of Patent: September 8, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Kroener, Christophe J. Layer, Petra Leber, Silvia M. Mueller
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Patent number: 8909994Abstract: A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals.Type: GrantFiled: December 3, 2013Date of Patent: December 9, 2014Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Juergen Haess, Michael K. Kroener, Silvia M. Mueller
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Patent number: 8892958Abstract: In a data processing system a plurality of signals associated with an operation are received during execution of the operation. In response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selects and outputs as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selects and outputs as the trace signal a second signal of the plurality of signals.Type: GrantFiled: June 15, 2012Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Juergen Haess, Michael K. Kroener, Silvia M. Mueller