Abstract: According to one aspect of the invention, a query request is received from a client application at a multithreaded graphics framework. The multithreaded graphics framework including a first thread configured to place graphics commands from the client application into a command queue and a second thread configured to dispatch the graphics commands from the command queue to a graphics processing unit (GPU) for execution. In response to the query request, the first thread is configured to store query information of the query request in a query block of memory that is separated from the command queue and notifying the second thread. In response to the notification, the second thread is configured to issue a query command to the GPU based on the query information retrieved from the query block, prior to dispatching remaining graphics commands pending in the command queue.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: According to one aspect of the invention, a query request is received from a client application at a multithreaded graphics framework. The multithreaded graphics framework including a first thread configured to place graphics commands from the client application into a command queue and a second thread configured to dispatch the graphics commands from the command queue to a graphics processing unit (GPU) for execution. In response to the query request, the first thread is configured to store query information of the query request in a query block of memory that is separated from the command queue and notifying the second thread. In response to the notification, the second thread is configured to issue a query command to the GPU based on the query information retrieved from the query block, prior to dispatching remaining graphics commands pending in the command queue.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: Methods and apparatuses to create and manage volatile graphics objects in a video memory are disclosed. An object is created and marked as volatile. The volatile object is stored in a video memory of a graphics subsystem. A volatile marking indicates that data for an object is not to be paged out from the video memory to make room for other data. The video memory space occupied by the volatile object is indicated as a volatile storage, in a data structure. Another object is written into at least a portion of the video memory space, which is occupied by the volatile object, without paging out data for the volatile object. In one embodiment, at least a portion of the volatile object is referenced or used while another object is formed. The volatile object may be discarded after being referenced or used to form another object.

Abstract: A multi-monitor computer system (10) includes a configuration address space (40) for software driven initialization and configuration. A monitor synchronization method (50) of this invention includes temporarily remapping multiple graphics chips (14, 18) to a same base address (46) so that attempts to write to a memory mapped register on one of the graphics chips, also writes the same register on the other graphics chips. Once the addresses are remapped, writing chip enabling data to an enabling register on one of the graphics chips causes enabling data to be written to all graphics chips at the same time, thereby synchronizing the vertical and horizontal sync signals generated by the graphics chips. Finally, remapping the graphics chips to their original base memory addresses allows the computer system to resume selective addressing of the graphics chips, which now provide synchronized vertical and horizontal sync signals to their respective monitors.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes selective pixel data fillers for writing either X or Y position pixel data to the internal SRAM devices. By selectively storing either X or Y position pixel data, the graphics processor is able to perform bit-block data transfers (blts) of pixel data to the internal SRAM thereby efficiently utilizing the local bandwidth of the internal SRAM.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates from a first clock domain a display list which includes poly parameter data for rendering the graphics primitives. A graphics processor which includes internal fetch and store unit stores and processes the polygon parameter data in a second clock domain different from the first clock domain. To ensure the complete processing of polygon data from the first clock domain in the second clock domain, the graphics processor includes a polygon data tracking logic for tracking the flow of the polygon data in the graphics processor. The polygon data tracking logic includes an up/down counter which up counts polygon data fetched in the graphics processor and down counts the polygon data when the polygon data is processed in the graphics processor.

Abstract: A texture value determining (TVD) circuit approximates non-homogenous 2nd order perspective texture mapping to provide texture for a polygon using linear interpolation and input parameters. The TVD circuit of the present invention includes a vertical walk subcircuit and an orthogonal walk subcircuit. The vertical walk subcircuit determines texture coordinates, u(a.sub.0,n) and v(a.sub.0,n) that represent the pixels along a vertical main slop of a triangle polygon. The orthogonal walk subcircuit determines texture coordinates, u(a.sub.m,n) and v(a.sub.m,n), for orthogonally walked polygon coordinate positions for which m>0. The orthogonally walked coordinate positions represent individual scan lines. The vertical walk subcircuit of the TVD circuit includes adders, latches, and accumulators. Each element of the vertical walk subcircuit receives a vertical main slope clock (n-clock) signal. An output of the vertical walk subsystem is computed based on the relationship,u(a.sub.0,n)=u(a.sub.0, n-1)+du.sub.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a pixel data striping control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic stripes the access into separate blocks of pixel data for each access which are then simultaneously accessed during a single data request cycle.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes internal fetch and store static random access memory (SRAM)devices for storing pixel fetched from an external memory device and processed in the graphics processor respectively. The graphics processor also includes a memory control logic which determines whether fetch and store requests by the graphics processor crosses an X boundary in the internal SRAM devices. If a fetch or store request crosses an X boundary, the memory control logic divides the access into two separate accesses which are then non-sequentially accessed during a single data request cycle. By non-sequentially fetching and storing data, the graphics processor is able to execute a single X crossing for multiple Y scan-line operations to fetch or store data internally.

Abstract: A process and implementing computer system for graphics applications in which polygons from a frame buffer, which may have three dimensional depth, color and other characteristics, are compactly reassembled and drawn to a fast memory for high speed and highly efficient processing. Polygons are divided into shaped segments which correspond to the shapes of the polygons. Corresponding memory storage references to the polygon objects themselves enable optimal processing efficiency and speed.