Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to he displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.

Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to he displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.

Abstract: Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a front-end synchronization signal that periodically increments a front-end counter. The front-end counter represents an unadjusted system time (UST). The media device obtains a frame of data to be displayed from a computer system. The media device also receives a back-end synchronization signal that periodically increments a back-end counter each time a frame of data is to be displayed. The back-end counter represents a media stream count (MSC). UST and MSC data are periodically transmitted to the computer system for analysis and use by a synchronization algorithm. Specifically, UST is transmitted to the computer system each time a frame of data is obtained, and a UST/MSC pair is transmitted to the computer system each time a frame of data is displayed.

Abstract: The present invention pertains to a clock generator that provides a plurality of dock outputs, each of which can be synchronized from one of several possible sets of references. Multiple frequency synthesizers are used to generate the clocks at the desired frequencies. These frequency synthesizers operate on the principle of dividing a supplied reference dock by an integer (I), plus a ratio (R/M), whereby there are approximately I plus (R/M) input clock cycles per output clock cycle. The output of a frequency synthesizer is a train of pulses with its duration equal to the period of the reference clock and at a rate equal to N/D=1/(I+R/M) times the reference clock rate. In order to generate an output signal with a more uniform duty cycle, the pulse train drives a toggle select circuit. The function of the toggle select circuit is to remove half of the phase quantization due to the limited frequency resolution of the reference dock.

Abstract: The present invention comprises an active shunt filter for filtering a power supply for noise sensitive devices. The active shunt filter includes a transistor and an op amp. A first resistor is coupled between the emitter of the transistor and a first power supply. A second resistor is coupled between the collector of the transistor and a ground. A third resistor is coupled between the base of the transistor and the output of the op amp. The output of the op amp controls the impedance of the transistor. The op amp is coupled to receive power from a second power supply. The negative input of the op amp is coupled to the emitter. The positive input of the op amp is coupled to the first power supply via a fourth resistor. A fifth resistor couples the positive input of the op amp to ground. A capacitor is also coupled between the positive input of the op amp and ground.

Abstract: A synchronization backbone for use in a computer system having a system board containing at least one central processing unit for processing digital data, a memory coupled to the system board for storing the digital data, a plurality of subsystems, and a bus structure for transmitting electrical signals between the system board, the memory, and the plurality of subsystems. The synchronization backbone provides the infrastructure that enables professional quality synchronization between the various subsystems. A clock generator is used to generate a system clock that is transmitted to each of the subsystems. The sample rate of a designated subsystem is used as a digital synchronization signal. The selected digital synchronization signal is then transmitted to each of the other subsystems. A synchronization circuit adjusts the sample rates associated with the other subsystems according to the digital synchronization signal and the system clock.