Abstract: A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface adapter that couples the host device to the network and allocating instances of a communication service on the network, to be provided via the adapter, to the processes. Upon receiving a request submitted by a given one of the processes to its respective doorbell address to access one of the allocated service instances, the adapter conveys the data over the network using the specified instance of the service, subject to verifying, based on the doorbell address to which the request was submitted, that the specified instance was allocated to the given process.

Abstract: A network interface adapter provides a host processor with two complementary modes of submitting descriptors to be executed by the adapter: a normal mode, in which the host writes descriptors to a system memory and rings an assigned doorbell to notify the adapter; and a priority mode, in which the host writes the descriptor itself to a doorbell address of the adapter. In the priority mode, the adapter is relieved of the need to read the descriptor from the memory, and can thus begin execution as soon as it has resources available to do so.

Abstract: A method for communication over a network includes receiving from a host processor a descriptor defining a message including message data to be sent over the network, and responsive to the descriptor, generating a sequence of packets each containing a respective portion of the message data. An indication is entered in a selected packet among the packets in the sequence, other than the final packet, requesting that a recipient of the packets acknowledge the selected packet. Following an interruption in the sequence of the packets subsequent to the selected packet, sending of the packets in the sequence resumes beginning after the selected packet.

Abstract: A network interface adapter includes an outgoing packet generator, adapted to generate an outgoing request packet for delivery to a remote responder responsive to a request submitted by a host processor and a network output port, coupled to transmit the outgoing request packet over a network to the remote responder. A network input port receives an incoming response packet from the remote responder, in response to the outgoing request packet sent thereto, as well as an incoming request packet sent by a remote requester. An incoming packet processor receives and processes both the incoming response packet and the incoming request packet, and causes the outgoing packet generator, responsive to the incoming request packet, to generate, in addition to the outgoing request packet, an outgoing response packet for transmission to the remote requester.

Abstract: An interface adapter for a packet network includes a first plurality of execution engines, coupled to a host interface so as to read from a memory work items corresponding to messages to be sent over the network, and to generate gather entries defining packets to be transmitted over the network responsive to the work items. A scheduling processor assigns the work items to the execution engines for generation of the gather entries. Switching circuitry couples the execution engines to a plurality of gather engines, which generate the packets responsive to the gather entries.

Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.

Abstract: A device for switching packets in a network includes a switching core and a plurality of ports, coupled to pass the packets from one to another through the switching core. The ports include, with respect to each packet among the packets switched by the device, a receiving port, coupled to receive the packet from a packet source, and a destination port, to which the packet is passed for conveyance to a packet destination. The ports also include one or more cache memories, respectively associated with one or more of the ports, each of the cache memories being configured to hold a forwarding database cache for reference by the receiving port with which the cache memory is associated in determining the destination port of the packet.

Abstract: A game system, incorporating co-existent interaction between a virtual character 20 and a user 10 in the real world, comprising a virtual character 20 in a computer sub-system 12,14 including a computer device 12 and means 38,40,42 for inputting real-world actions of a user in the real world into said sub-system 12,14, whereby actions of a user in the real world, at a pre-chosen real world location 36, other than correlative movements, are recorded and inputted into the computer sub-system and influence the character 20 in the virtual world 16.

Abstract: A photo-lithographic mask includes a flexible, optically transparent body having an optically transmissive first surface for receiving an optical signal, and a second surface opposite the first surface having grooves for internally reflecting first portions of the optical signal and for allowing second portions of the optical signal to be transmitted through the second surface when the second surface is pressed against a wafer. The body consists essentially of silicone. The grooves have a saw tooth profile that are configured at an angle that exceeds the critical angle of the silicone with respect to the direction of the incoming optical signal.

Abstract: The present invention provides a cap for a hermetically sealed container, said cap providing a visually observable indication of elapsed time from the opening of the seal of said container, said cap including means for releasing a chemical which effects a color change in a chamber formed therein, said chamber being provided with a transparent section for viewing the contents thereof and said released chemical effecting a cumulative color change of said section with time, the arrangement being such that manipulation of said cap to open said container and said seal effects activation of said releasing means.

Abstract: A method of direct memory access (DMA) includes receiving a first notification at a DMA engine that a first list of descriptors has been prepared, each of the descriptors in the list including an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link. The DMA engine reads and executes the descriptors in the first list. When the DMA engine receives a second notification that a second list of the descriptors has been prepared, it rereads at least a part of the final descriptor in the first list to determine a changed value of the link, indicating a first descriptor in the second list. It then reads and executes the descriptors in the second list responsive to the changed value of the link.

Abstract: A method for link-level flow control includes establishing a plurality of logical links over a physical link between a transmitting entity and a receiving entity in a network. Respective maximum limits of transmission credits are assigned to the logical links, the credits corresponding to space available to the links in a dynamically allocable portion of a receive buffer at the receiving entity, such that a sum of the maximum limits for all of the logical links corresponds to an amount of space substantially larger than a total volume of the space in the dynamically allocable portion of the receive buffer.

Abstract: A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a memory associated with a central processing unit (CPU), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

Abstract: The invention provides a water filtration vessel of the type having an upper reservoir for receiving tap water, a lower reservoir for storing filtered water and a filter-retaining passageway connecting between the upper and the lower reservoirs, further having a dispenser, mounted in communication with the lower reservoir for controllably adding a prequantified amount of a comestible additive to the filtered water.

Abstract: A multiprocessor computer system which maintains cache coherency includes first and second microprocessors each having an associated cache memory storing lines of data. Each line of data has associated protocol bits that indicate a protocol state consistent with write-through, write-back, or write-once cache coherency policies that are selected via a protocol selection terminal for different system configurations. In one configuration, the output and external address terminals of the first microprocessor are coupled to the external and output address terminals, respectively, of the second microprocessor. This configuration enables each microprocessor to snoop memory cycles to main memory initiated by the other microprocessor so that it can be readily determined if a particular cache has the latest version of data.

Abstract: An interactive multiple player game system including at least two playing devices communicating over an ad-hoc, wireless, all-to-all broadcast network. A playing device includes a processor for running a game scenario common to all of the playing devices within the network, a player controlled interface for enabling a player action within the game scenario, a transmitter for transmitting the player action over the network, a receiver for receiving player actions from other playing devices transmitting over the network, and a display for displaying at least a portion of the game scenario. The interactive multiple player game system can further include a play station device and an interface apparatus for. interfacing between the play station device and the playing devices.

Abstract: A processor and method implemented in a processor, having a pipeline and trap generation capabilities, for indicating a pipelined instruction and for generating a trap upon modification of the pipeline. Improved trap handling capabilities and improved overall system performance is provided by reducing unnecessary saving and restoring of the pipeline during certain trap handling procedures, such as those that do not modify the state of the pipeline.

Abstract: An improvement in a microprocessor having a cache memory providing strong and weak write ordering modes. The microprocessor includes a terminal for receiving a signal indicating whether an external write buffer is empty and an internal signal indicating whether an internal write buffer is empty. Operation of the microprocessor is halted in the strong ordering mode if the write buffers are not empty and a hit condition occurs during a write cycle until the buffers are empty.

Abstract: An improved cache memory for use with a microprocessor. A line buffer which stores a tag and offset field and the corresponding line of data is employed. Valid bits are associated with different potions of the data stored in the line buffer. Thus during a line fill, by way of example, an instruction may be read from the line buffer before the entire line is filled from main memory.

Abstract: An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.