Abstract: An electric vehicle drive unit includes an electric motor generating a torque. An input differential splits the torque into a first torque created by a first side gear and a second torque created by a second side gear. A first pinion gear shaft assembly receives the first torque and has a first pinion gear. A second pinion gear shaft assembly receives the second torque and has a second pinion gear. A first stage transfer gear assembly has a first, a second, a third, and a fourth transfer gear. A first stage speed reduction meshes the first pinion gear with the first transfer gear and the third transfer gear, and meshes the second pinion gear, the second transfer gear and the fourth transfer gear. A second stage gear assembly engages the first stage transfer gear assembly and includes a first final drive gear and a second final drive gear.

Abstract: A number of variations disclosed may include a product which may include a carrier having piloting features for assembling multiple gear drives for use in an electric drive unit of a vehicle. A number of variations disclosed may include a method of assembling a portion of an electric drive unit utilizing a gear piloting carrier having piloting features for assembling multiple gear drives.

Abstract: A pool-side, unplumbed, solar powered treatment system configured to monitor pool water and selectively introduce a plurality of different chemicals through individual pumps and feed lines to a return line to the pool. The present treatment system uses oxidation reduction potential, ORP, as a surrogate for chlorine/bromine/other oxidizer and pH probes to monitor water quality in real time and dispense appropriate amounts of chemicals to maintain a predetermined chemistry in a pool. The system introduces the chemicals into filtered pool water through a venturi or eductor.

Abstract: Compact electric drive units and vehicles with such drive units are provided. An exemplary electric drive unit includes an electric motor configured to provide an electric motor torque; an input differential configured to split the electric motor torque into a first path and a second path; a final drive gear on each path; a pinion gear on each path; and a rear transfer shaft assembly and a front transfer shaft assembly on each path. Further, each pinion gear is configured to transfer torque to a respective rear transfer shaft assembly and a respective front transfer shaft assembly, and the respective rear transfer and front transfer shaft assemblies are configured to transfer torque to the respective final drive gear.

Abstract: An insulative packaging for cold chain marketplace. The insulative packaging includes a base unit, a wall unit, and a top unit, which together form an enclosure. Each the base unit, the wall unit, and the top unit has an inflatable liner, one or more insulative sheets, and a radiant barrier. The inflatable liner can be folded and the one or more insulative sheets can be sandwiched between the two folds of the inflatable liner. An article to be protective can be placed within the enclosure and insulative packaging can provide 360-degree insulation and protection.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

Abstract: An insulative packaging for cold chain marketplace. The insulative packaging includes a base unit, a wall unit, and a top unit, which together form an enclosure. Each the base unit, the wall unit, and the top unit has an inflatable liner, one or more insulative sheets, and a radiant barrier. The inflatable liner can be folded and the one or more insulative sheets can be sandwiched between the two folds of the inflatable liner. An article to be protective can be placed within the enclosure and insulative packaging can provide 360-degree insulation and protection.

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

Abstract: In a method of forming a coated bag for pre-treating an item stored in the bag, a bag is provided, having a sidewall extending from a closed bottom end to an open top end and defining an interior surface of a cavity. The bag is expanded from a flattened condition to an expanded condition. At least one adhesive dispenser is inserted through the open top end of the bag into the cavity. An adhesive is applied from the at least one inserted adhesive dispenser to form an adhesive coating on the interior surface of the cavity. A particulate dispenser is inserted through the open top end of the bag into the cavity. A particulate is discharged from the inserted particulate dispenser to embed the particulate in the adhesive coating. The adhesive coating is dried to retain the embedded particulate on the interior surface of the sidewall.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Abstract: Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.

Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.

Abstract: Methods, systems, and devices for refresh-related activation in memory are described. A memory device may conduct a refresh operation to preserve the integrity of data. A refresh operation may be associated with a refresh time where the memory device is unable to execute or issue any commands (e.g., access commands). By posting (e.g., saving) one or more commands and/or row addresses during the refresh time, the memory device may be configured to execute the saved commands and/or re-open one or more rows associated with the saved row addresses at a later time (e.g., upon completion of the refresh operation). Accordingly, fewer commands may be issued to activate the memory cells after the refresh time.

Abstract: Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.