Abstract: A hash accelerator is provided that receives a hash key value from a processor core, determines a main memory address storing a hash table entry corresponding to the hash key value, and causes the hash table entry to be stored in a cache memory accessible by the processor core. The hash accelerator is configured to execute the same hash function that the processor core executes, and if the hash accelerator is faster than the software executing on the processor core, the hash table entry can be available to the core processor from cache memory by the time the processor core attempts to access the entry. This avoids a cache miss by the processor core, thereby improving overall efficiency of routines executed by the processor core.

Abstract: A hash accelerator is provided that receives a hash key value from a processor core, determines a main memory address storing a hash table entry corresponding to the hash key value, and causes the hash table entry to be stored in a cache memory accessible by the processor core. The hash accelerator is configured to execute the same hash function that the processor core executes, and if the hash accelerator is faster than the software executing on the processor core, the hash table entry can be available to the core processor from cache memory by the time the processor core attempts to access the entry. This avoids a cache miss by the processor core, thereby improving overall efficiency of routines executed by the processor core.

Abstract: A data processing system can comprise a first module having a workspace and configured to execute a task that can request access to a frame in a system memory, a queue manager configured to store a frame descriptor which identifies the frame in the system memory, and a memory access engine coupled to the first module and the queue manager. The memory access engine copies requested segments of the frame to the workspace and has a working frame unit to store a segment handle identifying a location and size of each requested segment copied to the workspace of the first module. The memory access engine tracks history of a requested segment by updating the working frame unit when the requested segment in the workspace is modified by the executing task.

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

Abstract: A data processing system can comprise a first module having a workspace and configured to execute a task that can request access to a frame in a system memory, a queue manager configured to store a frame descriptor which identifies the frame in the system memory, and a memory access engine coupled to the first module and the queue manager. The memory access engine copies requested segments of the frame to the workspace and has a working frame unit to store a segment handle identifying a location and size of each requested segment copied to the workspace of the first module. The memory access engine tracks history of a requested segment by updating the working frame unit when the requested segment in the workspace is modified by the executing task.

Abstract: The present disclosure provides system and method embodiments for a status register comprising a plurality of bits, where each of the plurality of bits of the status register is associated with one of a plurality of entities. A trigger mechanism is configured to write a trigger data pattern to the status register, where the trigger data pattern comprises a first state value for each of the plurality of bits of the status register. A capture mechanism is configured to write a second state value to each bit of the status register that is associated with an entity that is presently associated with a first type of entity status information, in response to a detection that the trigger data pattern is written to the status register.

Abstract: The present disclosure provides system and method embodiments for a status register comprising a plurality of bits, where each of the plurality of bits of the status register is associated with one of a plurality of entities. A trigger mechanism is configured to write a trigger data pattern to the status register, where the trigger data pattern comprises a first state value for each of the plurality of bits of the status register. A capture mechanism is configured to write a second state value to each bit of the status register that is associated with an entity that is presently associated with a first type of entity status information, in response to a detection that the trigger data pattern is written to the status register.

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.