Abstract: Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

Abstract: Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.

Abstract: Predicting local layout effects using a variational autoencoder with integrated regression and classification network including identifying a vector of features and a vector of output metrics from a dataset; performing basic training of a neural network machine learning variational autoencoder (VAE) combined with a regression network using the vector of features and the vector of output targets constrained to a latent space of the VAE; performing interpolation training of the VAE and combined regression network; determining a set of influential features of an integrated circuit layout based on an input gradient using an output of the VAE and combined regression network with interpolation training; using the set of influential features as input into a parallel neural network to generate a function for each influential feature; and creating a compact model to calculate local layout effects based on the functions for each influential feature.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

Abstract: Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: Systems and methods to place latches during hierarchical integrated circuit development obtain an initial floor plan indicating a blocked region, two or more regions, and initial locations of components including the latches. A method includes identifying a subset of the latches that belong to a vector as a vector of latches, the subset of the latches being single-bit latches that must be placed in a same one of the two or more regions, and identifying a center of gravity (COG) of the vector of latches, the COG being a mean of geometric points corresponding with the subset of the latches. All of the subset of the latches are placed at the COG to generate an intermediate floor plan based on determining that the COG is not in the blocked region. A final design of the integrated circuit that is obtained based on the intermediate floor plan is provided for fabrication.

Abstract: Methods, systems and computer program products for providing improved placement and connectivity of local clock buffer controllers are provided. Aspects include determining positions of a plurality of centroid locations within a circuit design based on positions of a plurality of latches within the circuit design. Aspects also include modifying the circuit design to place a local clock buffer controller at each of the plurality of centroid locations within the circuit design. Aspects also include connecting each of a plurality of local clock buffers within the circuit design to a nearest local clock buffer controller.