Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325. The system CPU initiates data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the graphics engine 325. In an alternate embodiment, the subsystem includes a subsystem master control unit or MCU to enable parallel or simultaneous operation of the Host XY unit and the graphics subsystem MCU.

Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.

Abstract: A graphics system includes a graphics controller for rendering polygons with a minimum number of steps and registers. The graphics controller includes a register file for receiving initial parameters for the polygon from a host. The graphics controller also includes a polygon engine for loading parameters from the register file and using these parameters to generate a starting X value for each scan line and a width value for each scan line to permit efficient rendering of the polygon without "edge walking" the polygon. The polygon engine includes a counter and a pair of accumulators for defining the number of orthogonal scan lines, the X start value for each scan line, and the width of each scan.

Abstract: A method for computing input parameters used in a non-homogeneous second order perspective texture mapping process using interpolation. The present invention receives a polygon primitive (e.g., triangle) including screen display coordinates and texture map coordinates for each vertex (vmin, vmid, and vmax). Based on vertex information including perspective weights, w, screen display coordinates and texture map coordinates are determined for midpoints (i and j) of the two triangle slopes opposite the triangle's major slope. Based on a determined quadratic equation of the triangle's major slope, screen coordinates and texture map coordinates are determined at several selected points (e.g., imain, jmain, and midmain) along the major slope that corresponds to the i, j, and vmid points. From these values, quadratic coefficients a1, a2, and du.sub.-- ortho.sub.-- add are computed and also quadratic coefficients b1, b2 and dv.sub.-- ortho.sub.-- add are computed. The above values, parameters u.sub.-- main, du.sub.

Abstract: A process and implementing computer system for graphics applications in which polygons from a frame buffer, which may have three dimensional depth, color and other characteristics, are compactly reassembled and drawn to a fast memory for high speed and highly efficient processing. Polygons are divided into shaped segments which correspond to the shapes of the polygons. Corresponding memory storage references to the polygon objects themselves enable optimal processing efficiency and speed.

Abstract: A graphics system includes a graphics controller for rendering polygons with a minimum number of steps and registers. A host processor generates a display list that includes only the values necessary for rendering a primitive. The graphics controller includes a register file for receiving the display list either directly from the host processor or from system memory in which the host processor stored the display list. The graphics controller also includes logic to decode operational codes to ascertain which values from the register file must be used for rendering a primitive and which values can be skipped. Only the necessary values are transmitted to polygon and texture engines also included within the graphics processor.

Abstract: Within a data processing system, data transfer between a host device and a slave device is accomplished with only one write operation. The write operation performed by the host device, such as a central processing unit, is performed to an alias destination address, which is related to the destination address by an offset number. The data included within the write operation includes the source address of the data to be transferred. Such a data transfer operation could be utilized to transfer data to a display adapter for display of video related data on a display device.