Abstract: Elicitors are applied to cultivated crops in order to improve plant productivity and/or harvestable crop value in agricultural and horticultural operations providing increased production of metabolites in cultivated plants.

Abstract: Concepts for acquiring information for identifying a security configuration for an application are proposed. In particular, the information is obtained by running the application in a development environment, detecting security requests made on behalf of the application, and then storing security information associated with the security requests in a security log. Using this concept, a security log may be obtained from which an appropriate security configuration may be determined.

Abstract: Concepts for acquiring information for identifying a security configuration for an application are proposed. In particular, the information is obtained by running the application in a development environment, detecting security requests made on behalf of the application, and then storing security information associated with the security requests in a security log. Using this concept, a security log may be obtained from which an appropriate security configuration may be determined.

Abstract: Elicitors are applied to cultivated crops in order to improve plant productivity and/or harvestable crop value in agricultural and horticultural operations providing increased production of metabolites in cultivated plants.

Abstract: Elicitors are applied to cultivated crops in order to improve plant productivity and/or harvestable crop value in agricultural and horticultural operations providing increased production of metabolites in cultivated plants.

Abstract: Elicitors are applied to cultivated crops in order to improve plant productivity and/or harvestable crop value in agricultural and horticultural operations providing increased production of metabolites in cultivated plants.

Abstract: The application is directed to non-destructive manipulation, removal and installation of a centrifugal pump impeller in a manner effective to maintain the original manufacture balanced condition of the impeller and other pump components. Tools are used at the drive end and the wet end of the centrifugal pump for manipulating, removal and installation of a pump impeller.

Abstract: The application is directed to non-destructive manipulation, removal and installation of a centrifugal pump impeller in a manner effective to maintain the original manufacture balanced condition of the impeller and other pump components. Tools are used at the drive end and the wet end of the centrifugal pump for manipulating, removal and installation of a pump impeller.

Abstract: A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Abstract: The invention relates to a roller mill, particularly intended for dressing ores. To reduce the energy demand for comminution and classifying a grinding product, a classifying device is positioned below the grinding area and to it is supplied the comminuted ground material under gravity action, as well as classifying air from an annular chamber in the lower region of the grinding bowl and which has at least one fine material outlet and coarse material outlet.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

Abstract: A technique is provided for use in computerized modeling of an electronic system. The technique bases simulation of the system's operation (e.g., timing operation) upon both actual physical characteristics of a part of the system, and hierarchical analysis-based models of the rest of the system.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

Abstract: A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.