Abstract: A laminating method. A structure that includes first and second dielectric layers respectively positioned on opposing surfaces of a thermally conductive layer is pressurized between 1000 and 3000 psi concurrent with being subjected to a thermal process, including the steps of: (a) heating the structure from ambient room temperature to a temperature between 670° F. to 695° F. in a heatup stage of duration 42 to 57 minutes; (b) after step (a), maintaining the structure at an approximately constant temperature between 670° F. and 695° F. in a dwell stage of duration 105 to 125 minutes; (c) after step (b), cooling the structure to 400° F. in a slow cool stage of duration of 120 to 150 minutes, wherein step (c) is performed after step (b); and (d) after step (3), cooling the structure to ambient room temperature in a rapid cool stage of duration less than 180 minutes.

Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.

Abstract: A method of forming a plurality of solid conductive bumps for interconnecting two conductive layers of a circuit board with substantially coplanar upper surfaces. The method comprises the steps of applying a continuous homogenous metal layer onto a dielectric substrate, applying a first photoresist and exposing and developing said first photoresist to define a pattern of conductive bumps, etching the metal layer exposed by said development to form said plurality of conductive bumps, removing said first photoresist, applying a second photoresist onto the metal layer, exposing and developing said second photoresist to define a pattern of conductive bumps and circuit lines; etching the metal layer exposed by said development to form a pattern of circuit lines in said metal layer; and removing said second photoresist. The methods of the present invention also provides for fabricating a multilayer circuit board and a metallic border for providing rigidity to a panel.