Patents by Inventor Michael KNABL
Michael KNABL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11955729Abstract: Embodiments of an antenna system and a method for operating an antenna are disclosed. In an embodiment, an antenna system includes a first ferrite element, a second ferrite element, a first coil wrapped around the first ferrite element, a second coil wrapped around the second ferrite element, a first antenna interface electrically coupled to the first coil, a second antenna interface electrically coupled to the second coil, and a conductor network connected between the first coil, the second coil, the first antenna interface, and the second antenna interface.Type: GrantFiled: March 25, 2022Date of Patent: April 9, 2024Assignee: NXP B.V.Inventors: Oliver Kronschläger, David Knabl, Andreas Merl, Michael Stark, Erich Merlin
-
Patent number: 11610817Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.Type: GrantFiled: March 19, 2021Date of Patent: March 21, 2023Assignee: Infineon Technologies Austria AGInventors: Andreas Kitzler, John Cooper, Jakob Simon Dohr, Michael Knabl, Matic Krivec, Daniel Pieber
-
Patent number: 11515264Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.Type: GrantFiled: May 24, 2019Date of Patent: November 29, 2022Assignee: Infineon Technologies AGInventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
-
Publication number: 20220359428Abstract: A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
-
Publication number: 20220301933Abstract: A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Inventors: Andreas Kitzler, John Cooper, Jakob Simon Dohr, Michael Knabl, Matic Krivec, Daniel Pieber
-
Publication number: 20220085174Abstract: A method of manufacturing a semiconductor device includes: providing a silicon carbide substrate that includes device regions and a grid-shaped kerf region laterally separating the device regions; forming a mold structure on a backside surface of the grid-shaped kerf region; forming backside metal structures on a backside surface of the device regions; and separating the device regions, wherein parts of the mold structure form frame structures laterally surrounding the backside metal structures.Type: ApplicationFiled: November 22, 2021Publication date: March 17, 2022Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
-
Patent number: 11211459Abstract: An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.Type: GrantFiled: December 16, 2019Date of Patent: December 28, 2021Assignee: Infineon Technologies AGInventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
-
Publication number: 20200194558Abstract: An auxiliary carrier and a silicon carbide substrate are provided. The silicon carbide substrate includes an idle layer and a device layer between a main surface at a front side of the silicon carbide substrate and the idle layer. The device layer includes a plurality of laterally separated device regions. Each device region extends from the main surface to the idle layer. The auxiliary carrier is structurally connected with the silicon carbide substrate at the front side. The idle layer is removed. A mold structure is formed that fills a grid-shaped groove that laterally separates the device regions. The device regions are separated, and parts of the mold structure form frame structures laterally surrounding the device regions.Type: ApplicationFiled: December 16, 2019Publication date: June 18, 2020Inventors: Andre Brockmeier, Guenter Denifl, Ronny Kern, Michael Knabl, Matteo Piccin, Francisco Javier Santos Rodriguez
-
Patent number: 10580753Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.Type: GrantFiled: July 21, 2017Date of Patent: March 3, 2020Assignee: Infineon Technologies AGInventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
-
Publication number: 20190363057Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.Type: ApplicationFiled: May 24, 2019Publication date: November 28, 2019Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
-
Publication number: 20190027464Abstract: According to an embodiment of a method of manufacturing a plurality of semiconductor devices on a wafer, the method includes forming a structure layer comprising a plurality of same semiconductor device structures and providing a protective layer on the structure layer. The protective layer on a first one of the plurality of semiconductor device structures differs from the protective layer on a second one of the plurality of semiconductor device structures.Type: ApplicationFiled: July 21, 2017Publication date: January 24, 2019Applicant: Infineon Technologies AGInventors: Martin Mischitz, Harald Huber, Michael Knabl, Claudia Sgiarovello, Caterina Travan, Andrew Wood
-
Patent number: 9698106Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.Type: GrantFiled: March 17, 2016Date of Patent: July 4, 2017Assignee: Infineon Technologies Austria AGInventors: Kae-Horng Wang, Francisco Javier Santos Rodriguez, Michael Knabl, Guenther Koffler
-
Publication number: 20160203979Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventors: Kae-Horng Wang, Francisco Javier Santos Rodriguez, Michael Knabl, Guenther Koffler
-
Patent number: 9318446Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.Type: GrantFiled: February 20, 2014Date of Patent: April 19, 2016Assignee: Infineon Technologies Austria AGInventors: Kae-Horng Wang, Francisco Javier Santos Rodriguez, Michael Knabl, Guenther Koffler
-
Patent number: 8841768Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber regionType: GrantFiled: July 23, 2012Date of Patent: September 23, 2014Assignee: Infineon Technologies AGInventors: Carsten Von Koblinski, Michael Knabl, Ursula Meyer, Francisco Javier Santos Rodriguez, Alexander Breymesser, Andre Brockmeier
-
Publication number: 20140264779Abstract: Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.Type: ApplicationFiled: February 20, 2014Publication date: September 18, 2014Applicant: Infineon Technologies Austria AGInventors: Kae-Horng Wang, Francisco Javier Santos Rodriguez, Michael Knabl, Guenther Koffler
-
Publication number: 20140021610Abstract: A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber regionType: ApplicationFiled: July 23, 2012Publication date: January 23, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Carsten VON KOBLINSKI, Michael KNABL, Ursula MEYER, Francisco Javier SANTOS RODRIGUEZ, Alexander BREYMESSER, Andre BROCKMEIER