Patents by Inventor Michael Kounavis

Michael Kounavis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210264274
    Abstract: Partitioning a deep neural network (DNN) model into one or more sets of one or more private layers and one or more sets of one or more public layers, a set of one or more private layers being at least one key in a cryptographic system; and deploying the partitioned DNN model on one or more computing systems.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Raizy Kellerman, Michael Kounavis, Omer Ben-Shalom, Alex Nayshtut, Oleg Pogorelik
  • Publication number: 20210266330
    Abstract: A data processing system includes technology to enable implicit integrity to be used for digital communications. That technology comprises a hardware processor and an implicit integrity engine (IIE) responsive to the processor. For instance, in response to the data processing system receiving a communication that contains a message, the IIE is to automatically analyze the communication to determine whether the message was sent with implicit integrity. If the message was sent with implicit integrity, the IIE is to automatically use a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message, and to automatically determine whether the message has low entropy, based on results of the pattern matching algorithm and a predetermined entropy threshold. If the message does not have low entropy, the IIE is to automatically determine that the message has been corrupted. Other embodiments are described and claimed.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Inventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
  • Patent number: 11082432
    Abstract: Before sending a message to a destination device, a source device automatically uses a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message. The pattern matching algorithm uses at least one pattern matching test to generate at least one entropy metric for the message. The source device automatically determines whether the message has sufficiently low entropy, based on results of the pattern matching algorithm. In response to a determination that the message does not have sufficiently low entropy, the source device automatically generates integrity metadata for the message and sends the integrity metadata to the destination device. However, in response to a determination that the message has sufficiently low entropy, the source device sends the message to the destination device without sending any integrity metadata for the message to the destination device. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
  • Patent number: 10949358
    Abstract: Embodiments are directed to providing a secure address translation service.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 16, 2021
    Assignee: INTEL CORPORATON
    Inventors: Michael Kounavis, David Koufaty, Anna Trikalinou, Rupin Vakharwala
  • Patent number: 10929527
    Abstract: Logic may implement implicit integrity techniques to maintain integrity of data. Logic may perform operations on data stored in main memory, cache, flash, data storage, or any other memory. Logic may perform more than one pattern check to determine repetitions of entities within the data. Logic may determine entropy index values and/or Boolean values and/or may compare the results to threshold values to determine if a data unit is valid. Logic may merge a tag with the data unit without expanding the data unit to create an encoded data unit. Logic may decode and process the encoded data unit to determine the data unit and the tag. Logic may determine value histograms for two or more entities, determine a sum of repetitions of the two or more entities, and compare the sum to a threshold value. Logic may determine that a data unit is valid or is corrupted.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Michael Kounavis, David Durham, Sergej Deutsch, Saeedeh Komijani, Amitabh Das
  • Patent number: 10855815
    Abstract: A method of data nibble-histogram compression can include determining a first amount of space freed by compressing the input data using a first compression technique, determining a second amount of space freed by compressing the input data using a second, different compression technique, compressing the input data using the compression technique of the first and second compression techniques determined to free up more space to create compressed input data, and inserting into the compressed input data, security data including one of a message authentication control (MAC) and an inventory control tag (ICT).
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Michael Kounavis, David M. Durham, Karanvir Grewal, Wenjie Xiong, Sergej Deutsch
  • Publication number: 20200327072
    Abstract: Methods and apparatus relating to secure-ATS (or secure Address Translation Services) using a version tree for replay protection are described. In an embodiment, memory stores data for a secured device. The stored data comprising information for one or more intermediate nodes and one or more leaf nodes. Logic circuitry allows/disallows access to contents of a memory region associated with a first leaf node from the one or more leaf nodes by a memory access request based at least in part on whether the memory access request is associated with a permission authenticated by the MAC of the first leaf node. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Michael Kounavis, Anna Trikalinou
  • Patent number: 10757227
    Abstract: A method of data nibble-histogram compression can include determining a first amount of space freed by compressing the input data using a first compression technique, determining a second amount of space freed by compressing the input data using a second, different compression technique, compressing the input data using the compression technique of the first and second compression techniques determined to free up more space to create compressed input data, and inserting into the compressed input data, security data including one of a message authentication control (MAC) and an inventory control tag (ICT).
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Michael Kounavis, David M. Durham, Karanvir Grewal, Wenjie Xiong, Sergej Deutsch
  • Patent number: 10755386
    Abstract: Median filtering of images is described using a directed search. In one example a method includes sliding a first window to a second position on an image to generate a second window where the first window overlaps the second window, determining a second histogram of pixel values by extracting a set of pixels from the first histogram and adding a set of pixels to the first histogram so that the second histogram has only pixels within the second window, determining a second median value of the pixel values using the second histogram by searching pixel values of the second histogram for the median starting at the median value of the first histogram, and repeating sliding the window determining a histogram and determining a median value until a complete median set of an area of interest of the image is determined.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventor: Michael Kounavis
  • Patent number: 10672401
    Abstract: Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Nikhil Pantpratinidhi, Gokcen Cilingir, Michael Deisher, Ohad Falik, Michael Kounavis
  • Publication number: 20200076924
    Abstract: A method of data nibble-histogram compression can include determining a first amount of space freed by compressing the input data using a first compression technique, determining a second amount of space freed by compressing the input data using a second, different compression technique, compressing the input data using the compression technique of the first and second compression techniques determined to free up more space to create compressed input data, and inserting into the compressed input data, security data including one of a message authentication control (MAC) and an inventory control tag (ICT).
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Inventors: Michael Kounavis, David M. Durham, Karanvir Grewal, Wenjie Xiong, Sergej Deutsch
  • Publication number: 20200076923
    Abstract: A method of data nibble-histogram compression can include determining a first amount of space freed by compressing the input data using a first compression technique, determining a second amount of space freed by compressing the input data using a second, different compression technique, compressing the input data using the compression technique of the first and second compression techniques determined to free up more space to create compressed input data, and inserting into the compressed input data, security data including one of a message authentication control (MAC) and an inventory control tag (ICT).
    Type: Application
    Filed: November 5, 2019
    Publication date: March 5, 2020
    Inventors: Michael Kounavis, David M. Durham, Karanvir Grewal, Wenjie Xiong, Sergej Deutsch
  • Publication number: 20200026661
    Abstract: Embodiments are directed to providing a secure address translation service.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 23, 2020
    Applicant: Intel Corporation
    Inventors: Michael Kounavis, David Koufaty, Anna Trikalinou, Rupin Vakharwala
  • Patent number: 10498865
    Abstract: A method of data nibble-histogram compression can include determining a first amount of space freed by compressing the input data using a first compression technique, determining a second amount of space freed by compressing the input data using a second, different compression technique, compressing the input data using the compression technique of the first and second compression techniques determined to free up more space to create compressed input data, and inserting into the compressed input data, security data including one of a message authentication control (MAC) and an inventory control tag (ICT).
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Michael Kounavis, David M. Durham, Karanvir Grewal, Wenjie Xiong, Sergej Deutsch
  • Patent number: 10496876
    Abstract: Specular light shadow removal is described for use in image de-noising. In one example a method includes placing a window on an image, determining a cumulative distribution function for the window, determining a destination histogram for the window, determining a cumulative distribution function for the destination histogram, replacing the intensity of a pixel with the smallest index for which the histogram distribution for the pixel is greater than the window distribution, repeating determining a cumulative distribution function, a destination histogram, and a cumulative distribution function and replacing the intensity for a plurality of windows of the image, and de-noising the image after repeating by applying a median filter to the image.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventor: Michael Kounavis
  • Publication number: 20190229889
    Abstract: In one example, an apparatus for Advanced Encryption Standard (AES) substitutions box (S-box) encryption includes an S-Box logic function and a MixColumns multiplication operation. The S-box logic function takes as input a state and is an 8-bit to 8-bit logic function, and wherein the S-box logic function is minimized such that an S-box round comprises nine not-and (NAND) levels and duplications of a logical product of the minimized S-box logic function are eliminated. The MixColumns multiplication operation comprises a plurality of factors that are exclusive ORed (XOR) with an output of the S-box round to obtain a scaled 16-byte output.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Applicant: INTEL CORPORATION
    Inventor: Michael Kounavis
  • Publication number: 20190229925
    Abstract: The present disclosure is directed to systems and methods for the secure transmission of plaintext data blocks encrypted using a NIST standard encryption to provide a plurality of ciphertext data blocks, and using the ciphertext data blocks to generate a Galois multiplication-based authentication tag and parity information that is communicated in parallel with the ciphertext blocks and provides a mechanism for error detection, location and correction for a single ciphertext data block or a plurality of ciphertext data blocks included on a storage device. The systems and methods include encrypting a plurality of plaintext blocks to provide a plurality of ciphertext blocks. The systems and methods include generating a Galois Message Authentication Code (GMAC) authentication tag and parity information using the ciphertext blocks.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Michael Kounavis, Sergej Deutsch, David M. Durham, Karanvir Grewal
  • Publication number: 20190220605
    Abstract: In one example an apparatus comprises a memory and a processor to create, from a first deep neural network (DNN) model, a first plurality of DNN models, generate a first set of adversarial examples that are misclassified by the first plurality of deep neural network (DNN) models, determine a first set of activation path differentials between the first plurality of adversarial examples, generate, from the first set of activation path differentials, at least one composite adversarial example which incorporates at least one intersecting critical path that is shared between at least two adversarial examples in the first set of adversarial examples, and use the at least one composite adversarial example to generate a set of inputs for a subsequent training iteration of the DNN model. Other examples may be described.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Applicant: Intel Corporation
    Inventors: Michael Kounavis, Antonios Papadimitriou, Anindya Paul, Micah Sheller, Li Chen, Cory Cornelius, Brandon Edwards
  • Publication number: 20190156183
    Abstract: The present disclosure is directed to systems and methods for the selective introduction of low-level pseudo-random noise into at least a portion of the weights used in a neural network model to increase the robustness of the neural network and provide a stochastic transformation defense against perturbation type attacks. Random number generation circuitry provides a plurality of pseudo-random values. Combiner circuitry combines the pseudo-random values with a defined number of least significant bits/digits in at least some of the weights used to provide a neural network model implemented by neural network circuitry. In some instances, selection circuitry selects pseudo-random values for combination with the network weights based on a defined pseudo-random value probability distribution.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: David M. Durham, Michael Kounavis, Oleg Pogorelik, Alex Nayshtut, Omer Ben-Shalom, Antonios Papadimitriou
  • Patent number: 10291394
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael Kounavis