Abstract: A method and system for use in a data processing system is proposed, wherein the Input Exponent is used already in the subblocks of the mantissa addition. Early in the flow of a cycle, there are parts of the Potential exponent result generated and put together using zero detect signals and carry select signals of the Carry Select Adder of the mantissa addition. For the addition of two floating point numbers this reduces the number of required logic gates in the timing critical path. This allows a faster cycle time and/or less latency and/or more complex functions. The method and system according to the invention can be applied to adders of different mantissa widths or different exponent widths as well as power of radix 2.