Patents by Inventor MICHAEL KRASNICKI
MICHAEL KRASNICKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11704448Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.Type: GrantFiled: July 26, 2021Date of Patent: July 18, 2023Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
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Patent number: 11657201Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a representation of said electronic design comprised at least in part of at least one analog portion, at least one specification of said electronic design, at least one manufacturing process variation of said at least one analog portion of said electronic design and at least one functional variation of said at least one analog portion of said electronic design. At least one set of valid states delimited by one of said at least one specification, said at least one manufacturing process variation and said at least one functional variation is then generated.Type: GrantFiled: May 10, 2021Date of Patent: May 23, 2023Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki
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Patent number: 11436883Abstract: Methods and systems are provided for pairing electronic devices. One method includes generating a code sequence for pairing an electronic device with an application executed by a processor of a controller, the controller being remote to the electronic device, and the electronic device and the controller interfacing with a server via a network connection. The code sequence includes a configuration mode portion indicating a role for a user of the controller, an invitation sequence having invitation code for the user and a random code portion. The method further includes receiving the code sequence by the electronic device; validating the code sequence by the electronic device using a key data structure; and pairing the electronic device to the controller for enabling the application to monitor and command the electronic device.Type: GrantFiled: July 8, 2019Date of Patent: September 6, 2022Assignee: Hampton Products International CorporationInventors: Jose Luis Vega, Michael Krasnicki, Howard Shen, Jon Fong Quan
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Publication number: 20210357539Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.Type: ApplicationFiled: July 26, 2021Publication date: November 18, 2021Inventors: Felicia James, Michael Krasnicki, Xiyuan WU
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Publication number: 20210264088Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a representation of said electronic design comprised at least in part of at least one analog portion, at least one specification of said electronic design, at least one manufacturing process variation of said at least one analog portion of said electronic design and at least one functional variation of said at least one analog portion of said electronic design. At least one set of valid states delimited by one of said at least one specification, said at least one manufacturing process variation and said at least one functional variation is then generated.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Felicia James, Michael Krasnicki
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Patent number: 11074373Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.Type: GrantFiled: April 14, 2020Date of Patent: July 27, 2021Assignee: Zipalog Inc.Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
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Patent number: 11003824Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.Type: GrantFiled: June 23, 2020Date of Patent: May 11, 2021Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki
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Patent number: 10963608Abstract: A computer implemented method of passive verification of an electronic design, includes the steps of receiving a first electronic design file of a first electronic design comprised at least in part of a mixed signal or analog system, the first electronic design file including at least one first system and first subsystem, collecting first input data from at least one first system input and first subsystem input, analyzing a first parameter of the first input data, receiving a second electronic design file of a second electronic design comprised at least in part of a mixed signal or analog system, the second electronic design file including at least one second system and second subsystem that are comparable in function to the at least one first system and first subsystem of the first electronic design file, collecting second input data from at least one second system input and second subsystem input of the second design file, analyzing the first parameter of the second input data, comparing the analysis of theType: GrantFiled: March 24, 2020Date of Patent: March 30, 2021Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki
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Publication number: 20200320242Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Felicia James, Michael Krasnicki
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Publication number: 20200242277Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: Felicia James, Michael Krasnicki, Xiyuan WU
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Publication number: 20200218843Abstract: A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog.Type: ApplicationFiled: March 24, 2020Publication date: July 9, 2020Inventors: Felicia James, Michael Krasnicki
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Patent number: 10691857Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.Type: GrantFiled: March 19, 2019Date of Patent: June 23, 2020Assignee: Zipalog, Inc.Inventors: Felicia James, Michael Krasnicki
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Patent number: 10621290Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stType: GrantFiled: August 9, 2019Date of Patent: April 14, 2020Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
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Patent number: 10599793Abstract: A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog.Type: GrantFiled: July 2, 2019Date of Patent: March 24, 2020Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki
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Publication number: 20200013246Abstract: Methods and systems are provided for pairing electronic devices. One method includes generating a code sequence for pairing an electronic device with an application executed by a processor of a controller, the controller being remote to the electronic device, and the electronic device and the controller interfacing with a server via a network connection. The code sequence includes a configuration mode portion indicating a role for a user of the controller, an invitation sequence having invitation code for the user and a random code portion. The method further includes receiving the code sequence by the electronic device; validating the code sequence by the electronic device using a key data structure; and pairing the electronic device to the controller for enabling the application to monitor and command the electronic device.Type: ApplicationFiled: July 8, 2019Publication date: January 9, 2020Applicant: HAMPTON PRODUCTS INTERNATIONAL CORPORATIONInventors: Jose Luis Vega, Michael Krasnicki, Howard Shen, Jon Fong Quan
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Publication number: 20190362032Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, a first stimulus parameter of the at least two stimulus parameters comprising an input to an input pin of the electronic circuit defined by the electronic design file, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least two stimulus parameter stored in at least one specification database and at least one measurement parameter stType: ApplicationFiled: August 9, 2019Publication date: November 28, 2019Inventors: FELICIA JAMES, MICHAEL KRASNICKI, XIYUAN WU
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Publication number: 20190325100Abstract: A computer implemented method of passive verification of an electronic design, comprising receiving an electronic design file of said electronic design comprised at least in part of a mixed signal or analog system including a plurality of subsystems. At least one analog subsystem of the plurality of subsystems has at least two design representations within the electronic design file that are intended to be equivalent for the at least one analog subsystem being simulated. First and second input subsystem data is collected for a first and second subsystem design representation of the at least two design representations from an analog stimulus to at least one input of the first and second subsystem design representation which is analog.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: FELICIA JAMES, MICHAEL KRASNICKI
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Patent number: 10402505Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlType: GrantFiled: July 19, 2017Date of Patent: September 3, 2019Assignee: ZIPALOG, INC.Inventors: Felicia James, Michael Krasnicki, Xiyuan Wu
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Publication number: 20190213293Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.Type: ApplicationFiled: March 19, 2019Publication date: July 11, 2019Inventors: Felicia James, Michael Krasnicki
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Patent number: D973518Type: GrantFiled: April 13, 2021Date of Patent: December 27, 2022Assignee: Lennox Industries Inc.Inventors: Surendran Ramasamy, Stephen J. Vendt, Arun Kunasekaran, Steve Lazar, Melissa Amoros, Michael Krasnicki, Bruce Lee