Patents by Inventor Michael Kroener

Michael Kroener has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200412036
    Abstract: A circuit arrangement having two interconnected high-frequency components, namely a first component and a second component, is described. A connection for transferring high-frequency signals is arranged between the first component and the second component. The connection includes at least one inner conductor, which is at least partially enclosed by an outer conductor. The inner conductor is connected to the first component and to the second component in order to transfer high-frequency signals. The second component includes a contact surface on a connecting surface and the inner conductor is pressed using a pressure force onto the contact surface, to establish a high-frequency connection between the first component and the second component.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 31, 2020
    Applicant: Tesat-Spacecom GmbH & Co. KG
    Inventors: Christian Arnold, Tobias Kässer, Michael Franz, Tobias Janocha, Andre Berger, Ralf Kröner, Ulrich Mahr, Benjamin Falk
  • Patent number: 10373868
    Abstract: According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: August 6, 2019
    Assignees: INFINEON TECHNOLOGIES AUSTRIA AG, TECHNISCHE UNIVERSITAET GRAZ
    Inventors: Martin Mischitz, Markus Heinrici, Michael Roesner, Oliver Hellmund, Caterina Travan, Manfred Schneegans, Peter Irsigler, Friedrich Kroener
  • Patent number: 9122517
    Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller
  • Publication number: 20130332501
    Abstract: A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: IBM Corporation
    Inventors: Maarten J. Boersma, Klaus Michael Kroener, Christophe J. Layer, Silvia M. Mueller
  • Patent number: 8495124
    Abstract: A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N?1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Adam B. Collura, Michael Kroener, Silvia Melitta Mueller
  • Patent number: 8407275
    Abstract: A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Michael Kroener, Silvia M. Mueller, Jochen Preiss
  • Patent number: 8346828
    Abstract: A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Maarten Boersma, Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Schelm
  • Patent number: 8291003
    Abstract: In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, K. Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Schelm
  • Patent number: 8278238
    Abstract: The present invention relates to light emitting compounds, especially to triplett emitters suitable for electrooptical applications. Compounds according to the invention are organometallic complexes of a metal, preferably Ir, having a backbone of one five-membered ring that is linked to a five- or six-membered ring, by an intermediate six-membered ring. These compounds are suitable for adaptation to the emission of light in the UV to NIR range by adaptation of atoms or groups within at least one of the five-membered or six-membered ring structures.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: October 2, 2012
    Assignees: Universitaet Bruanschweig, BASF Aktiengesellschaft
    Inventors: Hans-Hermann Johannes, Wolfgang Kowalsky, Sven Ammermann, Michael Kroener, Ute Jana Weinaug
  • Publication number: 20110320512
    Abstract: A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N?1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven R. Carlough, Adam B. Collura, Michael Kroener, Silvia Melitta Mueller
  • Patent number: 8032854
    Abstract: A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Maarten Boersma, Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Schelm
  • Patent number: 7840622
    Abstract: Method to convert a hexadecimal floating point number (H) into a binary floating point number by using a Floating Point Unit (FPU) with fused multiply add with an A-register a B-register for two multiplicand operands and a C-register for an addend operand, wherein a leading zero counting unit (LZC) is associated to the addend C-register, wherein the difference of the leading zero result provided by the LZC and the input exponent (E) is calculated by a control unit and determines based on the Raw-Result-Exponent a force signal (F) with special conditions like ‘Exponent Overflow’, ‘Exponent Underflow’, and ‘Zero Result’.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: November 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Guenter Gerwig, Klaus Michael Kroener
  • Patent number: 7730117
    Abstract: A system for performing floating point arithmetic operations including an input register adapted for receiving an operand. The system also includes a mechanism for performing a shift or masking operation in response to determining that the operand is in an un-normalized format. The system also includes instructions for performing single precision incrementing of the operand in response to determining that the operand is single precision, that the operand requires the incrementing based on the results of a previous operation and that the previous operation did not perform the incrementing. The operand was created in the previous operation. The system further includes instructions for performing double precision incrementing of the operand in response to determining that the operand is double precision, that the operand requires the incrementing based on the results of the previous operation and that the previous operation did not perform the incrementing.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Juergen Haess, Michael Kroener, Martin S. Schmookler, Eric M. Schwarz, Son Dao-Trong
  • Patent number: 7716266
    Abstract: A method and system for performing a binary mode and hexadecimal mode Multiply-Add floating point operation in a floating point arithmetic unit according to a formula A*C+B, wherein A, B and C operands each have a fraction and an exponent part expA, expB and expC and the exponent of the product A*C is calculated and compared to the exponent of the addend under inclusion of an exponent bias value dedicated to use unsigned biased exponents, wherein the comparison yields a shift amount used for aligning the addend with the product operand, wherein a shift amount calculation provides a common value CV for both binary and hexadecimal according to the formula (expA+expC?expB+CV).
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Son Dao Trong, Juergen Haess, Klaus Michael Kroener, Eric M. Schwarz
  • Publication number: 20100100713
    Abstract: A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 22, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, Michael Kroener, Silvia M. Meuller, Jochen Preiss
  • Publication number: 20100095099
    Abstract: A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 15, 2010
    Applicant: International Business Machines Corporation
    Inventors: Maarten Boersma, Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Schelm
  • Publication number: 20100063987
    Abstract: In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 11, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten J. Boersma, K. Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Schelm
  • Publication number: 20100058266
    Abstract: A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 4, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Maarten Boersma, Michael Kroener, Petra Leber, Silvia M. Mueller, Jochen Preiss, Kerstin Schelm
  • Publication number: 20090165846
    Abstract: The present invention relates to light emitting compounds, especially to triplett emitters suitable for electrooptical applications. Compounds according to the invention are organometallic complexes of a metal, preferably Ir, having a backbone of one five-membered ring that is linked to a five- or six-membered ring, by an intermediate six-membered ring. These compounds are suitable for adaptation to the emission of light in the UV to NIR range by adaptation of atoms or groups within at least one of the five-membered or six-membered ring structures.
    Type: Application
    Filed: September 7, 2006
    Publication date: July 2, 2009
    Applicants: UNIVERSITAET BRAUNSCHWEIG, BASF SE
    Inventors: Hans-Hermann Johannes, Wolfgang Kowalsky, Sven Ammermann, Michael Kroener, Ute Jana Weinaug
  • Patent number: 7461117
    Abstract: The invention proposes a Floating Point Unit (1) with fused multiply add, with one addend operand (eb, fb) and two multiplicand operands (ea, fa; ec, fc), with a shift amount logic (2) which based on the exponents of the operands (ea, eb and ec) computes an alignment shift amount, with an alignment logic (3) which uses the alignment shift amount to align the fraction (fb) of the addend operand, with a multiply logic (4) which multiplies the fractions of the multiplicand operands (fa, fc), with a adder logic (5) which adds the outputs of the alignment logic (3) and the multiply logic (4), with a normalization logic (6) which normalizes the output of the adder logic (5), which is characterized in that a leading zero logic (7) is provided which computes the number of leading zeros of the fraction of the addend operand (fb), and that a compare logic (8) is provided which based on the number of leading zeros and the alignment shift amount computes select signals that indicate whether the most significant bits of t
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Son Dao Trong, Juergen Haess, Christian Jacobi, Klaus Michael Kroener, Silvia Melitta Mueller, Jochen Preiss