Abstract: At a simulation client, a design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a plurality of count event counters that count occurrences of count events in the design during stimulation by the testcase. At multiple intervals during stimulation of the HDL simulation model by the testcase, the simulation client records count values of the plurality of count event counters. The simulation client determines, for each of the multiple intervals, a temporal statistic regarding the count values of the plurality of count event counters and outputs a report containing temporal statistics for the multiple intervals.

Abstract: A design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and the simulation includes counting occurrences of the count event in the count event counter to obtain a count event value. A threshold is also established for an aggregate count event value for the count event counter. After completion of the testcase, a determination is made whether addition of the count event value to the aggregate count event value for the count event counter would cause the aggregate count event value to exceed the threshold. If not, the count event value is recorded in a testcase data storage area, and the count event value is accumulated in the aggregate count event value. If so, the count event value is discarded without recording the count event value in the testcase data storage area.

Abstract: The exemplary embodiments provide a computer implemented method, apparatus, and computer usable program code for calculating the expected behavior of a group of hardware verification test cases. Batch simulation parameters are configured. A test case is submitted for evaluation. Historical performance data for test cases associated with the submitted test case is gathered. A set of performance statistics for the submitted test case is generated based on the historical performance data and the configured batch simulation parameters. A set of values for the submitted test is generated based on the generated performance statistics for the submitted test case and the historical performance data. The generated set of values and the generated set of performance statistics for the submitted test case are displayed to a user.

Abstract: A design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a count event counter for a count event in the design, and the simulation includes counting occurrences of the count event in the count event counter to obtain a count event value. A threshold is also established for an aggregate count event value for the count event counter. After completion of the testcase, a determination is made whether addition of the count event value to the aggregate count event value for the count event counter would cause the aggregate count event value to exceed the threshold. If not, the count event value is recorded in a testcase data storage area, and the count event value is accumulated in the aggregate count event value. If so, the count event value is discarded without recording the count event value in the testcase data storage area.

Abstract: At a simulation client, a design is simulated utilizing a hardware description language (HDL) simulation model by stimulating the HDL simulation model with a testcase. The HDL simulation model includes instrumentation not forming a portion of the design that includes a plurality of count event counters that count occurrences of count events in the design during stimulation by the testcase. At multiple intervals during stimulation of the HDL simulation model by the testcase, the simulation client records count values of the plurality of count event counters. The simulation client determines, for each of the multiple intervals, a temporal statistic regarding the count values of the plurality of count event counters and outputs a report containing temporal statistics for the multiple intervals.

Abstract: The exemplary embodiments provide a computer implemented method, apparatus, and computer usable program code for calculating the expected behavior of a group of hardware verification test cases. Batch simulation parameters are configured. A test case is submitted for evaluation. Historical performance data for test cases associated with the submitted test case is gathered. A set of performance statistics for the submitted test case is generated based on the historical performance data and the configured batch simulation parameters. A set of values for the submitted test is generated based on the generated performance statistics for the submitted test case and the historical performance data. The generated set of values and the generated set of performance statistics for the submitted test case are displayed to a user.

Abstract: A system for selecting a test case. A test case with a high score is selected. A simulation job is run on a device under test on a plurality of processors using the selected test case. Simulation performance and coverage data is collected for the selected test case and the collected simulation performance and coverage data is stored in a database.