Abstract: Systems, methods, architectures, mechanisms, tools, and apparatus providing design for testability (DFT) to rapidly estimate a number of faults made untestable by a given circuit signal being either in the X/Z logic state, uncontrollable, or unobservable, and to iteratively configure mechanisms for insertion of test point structure within a circuit under test (CUT) such as a digital circuit including a large number of sequential logic, combinational logic, latches, clocking/timing devices, and the like. Various embodiments contemplate several iterations to achieve a desired testing solution, illustratively (i) a first pass to eliminate uninitialized flip-flops and latches using blockers; (ii) a second pass to estimate the number of lost faults caused by each untestable site; and (iii) a final pass to select only the most essential test point sites using measures of Entropy, Entropy Gain, and/or Entropy Derivative.

Abstract: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF.

Abstract: Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF.

Abstract: The present invention relates to a method and system for detecting defects within an integrated circuit in which one or more parameters of a classifier are determined by graphical evaluation of IDDQ current measurements. Parameters of the classifier can include a number of bands for a good integrated circuit, a width of a band for a good chip, a width ratio between any two bands for a good integrated circuit, a separation between bands for a good integrated circuit, a separation ratio between any two bands for a good integrated circuit, a maximum slope for a good band, a variation in a band width for a good band, a maximum IDDQ value for a chip, a minimum IDDQ value for a chip, a mean of a band of a chip, a standard deviation of a band of a chip, a lack of activity of IDDQ measurements conducted in the integrated circuit, noise in the IDDQ measurements conducted in the integrated circuit and glitches in the IDDQ measurements conducted in the integrated circuit.

Abstract: The present invention relates to a method and system for detecting defects within an integrated circuit in which one or more parameters of a classifier are determined by graphical evaluation of IDDQ current measurements. Parameters of the classifier can include a number of bands for a good integrated circuit, a width of a band for a good chip, a width ratio between any two bands for a good integrated circuit, a separation between bands for a good integrated circuit, a separation ratio between any two bands for a good integrated circuit, a maximum slope for a good band, a variation in a band width for a good band, a maximum IDDQ value for a chip, a minimum IDDQ value for a chip, a mean of a band of a chip, a standard deviation of a band of a chip, a lack of activity of IDDQ measurements conducted in the integrated circuit, noise in the IDDQ measurements conducted in the integrated circuit and glitches in the IDDQ measurements conducted in the integrated circuit.

Abstract: The present invention relates to a method and apparatus for testing analog and mixed analog and digital circuits in which test waveforms are generated for testing the analog circuit. The analog circuit can be represented by a directed circuit graph. The directed circuit graph represents nodes of components of the circuit under test connected by directed edges for components having inputs or outputs which effect other components and undirected edges for components in the circuit that are bidirectional. For example, undirected edges are assigned to bidirectional elements such as resistors and capacitors and directed edges are assigned to transistors. The directed graph is partitioned into partitions that carry a signal from the primary inputs toward the primary outputs in the circuit under test. Feedback and local feedback are captured in a single partition. The partition of a faulty component is determined and the operating point of the partition is established to activate the fault.

Abstract: This invention relates to a method and apparatus for combined stuck-fault testing and partial scan delay-fault built-in self testing (BIST). For partial scan delay-fault BIST, the circuit is modeled for breaking all flip-flop feedback cycles in the circuit. A selection of flip-flops to be scanned to break all sequential cycles is determined from an optimal feedback vertex set. A digest, devour and tidy-up (DDT) heuristic can be used on a weighted signed graph formed from an S-graph of the circuit to determine an optimal feedback vertex set. Determined partial scan delay fault BIST hazards can be removed from the circuit by inserting parity flippers to invert selected paths during testing. The same DDT heuristic can be used to determine optimal placement of the parity flippers in the circuit.

Abstract: The present invention relates to a method and apparatus for generating test patterns to test an analog or mixed signal circuit. A signal flow graph of the analog circuit is determined. The signal flow graph is inverted and reverse simulated with good and bad outputs to determine component tolerances of the circuit given circuit output tolerances. The inverted signal flow graph is backtraced from analog outputs to obtain analog input sinusoids which justify the analog outputs.

Abstract: This invention relates to a method and apparatus for robust delay fault testing of integrated circuits (IC) with built-in self-testing. For the method, hazardous nodes of the IC are determined. Thereafter, the topology of the IC can be modified to include a cut-point at hazardous nodes of the circuit. Input of the IC to the cut-point is diverted to an observation point. An out-put multi-input signature register (MISR) at the observation point generates a first signature. An output MISR provides a second signature for outputs to the IC. During testing, a hazard-free input pattern is applied to the IC and the generated first and second signatures are compared to known correct signatures.