Abstract: A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.

Abstract: The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.

Abstract: A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.

Abstract: A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a under test (DUT) is coupled to both the gold processor and the TAP. Test signals are simultaneously provided to both the gold processor and the DUT such that the gold processor and the DUT operate in synchronous functional lockstep. The TAP may also input test signals into the gold processor and DUT simultaneously and access data from each of these processors through separate test data out (TDO) connections. Test output data accessed from the gold processor may be compared to test output data accessed from the DUT to determine if any differences are present. The comparison data generated may then be used for analysis purposes.

Abstract: A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a device under test (DUT) is coupled to both the gold processor and the TAP. In the first mode, the TAP provides test signals to both the gold processor and the DUT while they operate in synchronous functional lockstep. In the second mode, the TAP provides signals to the gold processor. In the third mode, the TAP provides test signals to the DUT. A host computer coupled to the interface control unit executes a software application to cause the TAP to drive test signals and to access test output data from the gold processor and the DUT. Test output data accessed from the gold processor may be compared to that accessed from the DUT to determine any differences. The comparison data generated may then be used for further analysis.

Abstract: A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.

Abstract: A method of operating a computer system. A first processor sends a first unit of binary information to an input/output (I/O) unit. The I/O unit then conveys the first unit of binary information to a functional unit in the computer system. A system response from the functional unit is then received by the I/O unit, which forwards the system response to the first processor. The system response is also stored in a first buffer. After a predetermined delay time has elapsed, the system response is then forwarded to the second processor.

Abstract: A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a device under test (DUT) is coupled to both the gold processor and the TAP. In the first mode, the TAP provides test signals to both the gold processor and the DUT while they operate in synchronous functional lockstep. In the second mode, the TAP provides signals to the gold processor. In the third mode, the TAP provides test signals to the DUT. A host computer coupled to the interface control unit executes a software application to cause the TAP to drive test signals and to access test output data from the gold processor and the DUT. Test output data accessed from the gold processor may be compared to that accessed from the DUT to determine any differences. The comparison data generated may then be used for further analysis.

Abstract: A system for testing a processor. The system includes a gold processor and a test access port (TAP). A processor that is a under test (DUT) is coupled to both the gold processor and the TAP. Test signals are simultaneously provided to both the gold processor and the DUT such that the gold processor and the DUT operate in synchronous functional lockstep. The TAP may also input test signals into the gold processor and DUT simultaneously and access data from each of these processors through separate test data out (TDO) connections. Test output data accessed from the gold processor may be compared to test output data accessed from the DUT to determine if any differences are present. The comparison data generated may then be used for analysis purposes.

Abstract: A system for capturing the data necessary for synthesizing an instruction stream for a microprocessor. An embodiment uses a microprocessor that is adapted to write its branch trace data to the main memory. This branch trace data includes whether the microprocessor took each conditional jump encountered during the execution of a program as well as the target location of each indirect jump. The preferred embodiment further includes a logic analyzer coupled to the primary expansion bus of the target computer system. The logic analyzer captures input/output reads and writes as well as DMA transactions to the main memory. Finally, a synthesis control card controls starting a data capture as well as facilitating the transfer of information from buffers in the main memory to the control computer system.

Abstract: An improved method for performing memory writes from a processor in a personal computer system is provided whereby single writes are combined into burst writes based on detection of suitable write operations in instruction code. In a preferred embodiment, the improved method is implemented in microcode. The method includes detecting multiple suitable write operations prior to the execution, collecting the data elements in a storage unit, and writing the data elements as burst write operations. Write operations that meet specific conditions for quantity of data elements to be written and specific conditions for destination address are suitable for bursting. The improved method can be implemented in existing personal computers, thereby improving system performance without requiring new software applications or a new computer board design.