Patents by Inventor Michael L. Dreyer

Michael L. Dreyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure
    Patent number: 5760476
    Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 2, 1998
    Assignee: Motorola, Inc.
    Inventors: Charles J. Varker, Michael L. Dreyer, Thomas E. Zirkle
  • Method for controlling electromigration and electrically conductive interconnect structure therefor
    Patent number: 5472911
    Abstract: A method and an electrically conductive interconnect structure (30) for controlling electromigration. The electrically conductive interconnect structure (30) comprises a groove (33) adjacent an electrically conductive interconnect (39). The electrically conductive interconnect (39) is patterned from a deposited layer of conductive material which contains global grain microstructures. Moreover, the electrically conductive interconnect (39) is patterned to have polycrystalline and single-grain segment lengths that are less than a length at which an electromigration flux fails to overcome a gradient-driven counter flux in a line segment. The groove (33) controls the polycrystalline and single-grain segment lengths to be less than the critical length, thereby reducing electromigration.
    Type: Grant
    Filed: September 2, 1994
    Date of Patent: December 5, 1995
    Assignee: Motorola, Inc.
    Inventors: Michael L. Dreyer, Charles J. Varker, Ganesh Rajagopalan
  • Semiconductor device interconnect layout structure for reducing premature electromigration failure due to high localized current density
    Patent number: 5461260
    Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: October 24, 1995
    Assignee: Motorola Inc.
    Inventors: Charles J. Varker, Michael L. Dreyer, Thomas E. Zirkle