Patents by Inventor Michael L. Fraser
Michael L. Fraser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10366986Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: GrantFiled: March 20, 2019Date of Patent: July 30, 2019Assignee: NXP USA, Inc.Inventors: Jason R. Fender, Michael L. Fraser, Frank E. Danaher
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Publication number: 20190221561Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: ApplicationFiled: March 20, 2019Publication date: July 18, 2019Inventors: Jason R. Fender, Michael L. Fraser, Frank E. Danaher
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Patent number: 10318447Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: GrantFiled: April 18, 2017Date of Patent: June 11, 2019Assignee: NXP USA, Inc.Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Patent number: 10283500Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: GrantFiled: September 29, 2017Date of Patent: May 7, 2019Assignee: NXP USA, Inc.Inventors: Michael L. Fraser, Frank E. Danaher, Jason R. Fender
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Publication number: 20180033787Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: ApplicationFiled: September 29, 2017Publication date: February 1, 2018Inventors: Michael L. FRASER, Frank E. DANAHER, Jason R. FENDER
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Patent number: 9780090Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: GrantFiled: October 19, 2015Date of Patent: October 3, 2017Assignee: NXP USA, INC.Inventors: Michael L. Fraser, Frank E. Danaher, Jason R. Fender
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Publication number: 20170220519Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a red Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Patent number: 9658971Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: GrantFiled: September 11, 2013Date of Patent: May 23, 2017Assignee: NXP USA, Inc.Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Publication number: 20170110451Abstract: A monolithic integrated circuit includes first and second pluralities of parallel-connected transistor elements (e.g., transistor fingers). To spread heat in the IC, the first and second pluralities of transistor elements are interleaved with each other and arranged in a first row. The IC also may include third and fourth pluralities of parallel-connected transistor elements arranged in a second row. The transistor elements in the first row may be series and shunt transistors of an RF switch transmit path, and the transistor elements in the second row may be series and shunt transistors of an RF switch receive path. During a transmit mode of operation, the series transistors in the transmit path and the shunt transistors in the receive path are closed. During a receive mode of operation, the shunt transistors in the transmit path and the series transistors in the receive path are closed.Type: ApplicationFiled: October 19, 2015Publication date: April 20, 2017Inventors: MICHAEL L. FRASER, FRANK E. DANAHER, JASON R. FENDER
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Publication number: 20150074319Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
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Patent number: 6300835Abstract: A power amplifier core (40) for amplifying RF signals is provided. The power amplifier core (40) includes a first string of FET cells (46) for amplifying the RF signal. The FET cell string includes at least two FET cells (46) connected in series with an output port (48) of the amplifier core. A bias network (44) coupled between an amplifier core input port (42) and the FET cells (46) couples the RF signal to the FET cells (46). The bias network (44) includes a bias capacitor (50) and a resistor network. The bias capacitor (50) is coupled to the input port (42) for AC coupling the RF signal to an associated FET cell (46) in the FET cell string. The resistor network is coupled from the bias capacitor (50) to the associated FET cell (46) for providing a DC bias to the associated FET cell (46).Type: GrantFiled: December 10, 1999Date of Patent: October 9, 2001Assignee: Motorola, Inc.Inventors: Warren L. Seely, Ronald F. Kielmeyer, Michael L. Fraser
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Patent number: 5777528Abstract: A series capacitance is included in both surface ground conductors of coplanar waveguide on an MMIC die. The capacitance compensates for the inductance of bond wires used for transitioning from microstrip line to coplanar waveguide. The capacitance is chosen to resonate with the inductance of the bond wires at the desired frequency. As a result, virtually all microstrip mode ground signal currents are transitioned from the ground plane of the microstrip line to the surface ground conductors of the coplanar waveguide. Microstrip modes affecting the coplanar waveguide are significantly reduced improving isolation between ports of the MMIC die.Type: GrantFiled: May 26, 1995Date of Patent: July 7, 1998Assignee: Motorola, Inc.Inventors: Lawrence James Schumacher, Michael L. Fraser
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Patent number: 5669068Abstract: A complimentary switched amplifier transceiver (10) is provided which offers performance advantages and reduces system complexity over conventional half-duplex transceivers by using complimentary switched amplifiers for eliminating switches. Power output to a channel transition (31) from a transmit amplifier (26) is not degraded by a switch insertion loss in a transmit mode. Receiver noise figure is not degraded due to the switch insertion loss from the channel transition (31) to a receive amplifier (27). Switch devices and their associated control lines are eliminated, reducing circuit complexity for complimentary switched amplifier circuits such as a combined amplifier switch (12) and a first bi-directional amplifier (22).Type: GrantFiled: July 3, 1995Date of Patent: September 16, 1997Assignee: Motorola, Inc.Inventors: Ronald F. Kielmeyer, Craig L. Fullerton, John D. Goshinska, Hugh R. Malone, Paul L. Brownlee, Richard J. Christensen, Michael L. Fraser