Abstract: A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to-recover the bitstream.

Abstract: A system and method are disclosed for parallel compression and decompression of a bitstream. For compression, the bitstream is separated into a plurality of components, and the components are encoded using a compression algorithm. Packets are then constructed from the encoded components. At least one packet is associated with each encoded component and comprises header information and encoded data. The packets are combined into a packetized encoded bitstream. For decompression, the packets are separated from the packetized encoded bitstream using the header information. The packets are then decoded in parallel using a decompression algorithm to recover the encoded data. The plurality of components are reconstructed from the recovered encoded data and combined to recover the bitstream.

Abstract: A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete.

Abstract: A method and arrangement for separating interleaved luminance and chrominance color space components data in a single data stream with minimum CPU intervention is provided. In the separating circuit, the separating circuit receives as input a series of graphics/video image data composed of interleaved luminance and chrominance color space components at successive clock cycles. The separating circuit directs selected bytes of the graphics/video image data representing the luminance color space component to a first path wherein luminance component data received at two successive clock cycles are combined. Likewise, selected bytes of the graphics/video image data representing the chrominance color space component are directed to a second path wherein chrominance component data received at two successive clock cycles are combined. Then, the combined luminance and chrominance component data are output alternately.

Abstract: Instruction methods for moving data between memory and a vector register file while performing data formatting. The methods are processed by a processor having a vector register file and a memory unit. The methods are useful in the graphics art because they allow more efficient movement and processing of raster formatted graphics data. The vector register file has a number of vector registers (e.g., 32) that each contain multi-bits of storage (e.g., 128 bits). In one class of instructions, eight byte locations within memory are simultaneously loaded into eight separate 16 bit locations within a register of the register file. The data can be integer or fraction and signed or unsigned. The data can also be stored from the register file back to memory. In a second class of instructions, alternate locations of a memory qaudword are selected and simultaneously loaded in the register file.

Abstract: This relates to a general purpose circuit that maximizes the computing power of a Unix workstation or other computer system for processing image or other data in accordance with a selected one or ones of several alternative compression and decompression algorithms. This dynamically allocates system memory for storage of both compressed and uncompressed data and ensures adequate compression and decompression rates.