Abstract: Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.

Abstract: A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure.

Abstract: A data processing system and method for substituting selected requests with substitute requests that perform the same or similar end function but achieve increased system performance are disclosed. Those requests that have a selected request characteristic are identified and converted or replaced with a predetermined substitute request. The substitute requests perform at least part of the function of the identified requests. The data processing system may include two or more processors, and the selected request characteristic may be that a write data packet of an identified write request was not changed by a first processor. A substitute request may update directory information associated with the identified write request but may not write to associated data packet to memory. The directory information can indicate whether identified memory locations are currently owned by a processor.

Abstract: A system and method for reducing data transfer delays in a transaction processing system is provided. The system includes a plurality of devices each having an associated local memory, and a supervisory memory module having a main storage module for storing data segments and a directory storage for maintaining ownership status of each data segment stored in the main storage module and the local memories. A second device makes a request for a data segment which is stored in a first local memory of a first device. A data transfer request for the requested data segment is transferred from the second device to the supervisory memory module, where the data transfer request includes an identifier requesting permission to modify the requested data segment. The requested data and a data transfer response is delivered to the second device upon receipt of the data transfer request, where the data transfer response provides modification privileges of the requested data segment to the second device.

Abstract: A system and method for providing direct transfers of data segments between devices having local memories without the need for first transferring the data to a central supervisory memory to maintain cache coherency. Direct data transfers are performed from a first local memory of a first device to a second local memory in a second device in a transaction processing system that includes a main memory to provide supervisory storage capability for the transaction processing system, and a directory storage for maintaining ownership status of each data segment of the main memory. A data transfer of a requested data segment is requested by the second device to obtain the requested data segment stored in the first local memory of the first device. The requested data segment is removed from the first local memory in response to the data transfer request, and is directly transferred to the second local memory of the second device.

Abstract: A method and apparatus for providing a multi-source reset for independent partitions within a multiprocessor computer system. In a system having at least two partitions wherein the at least two partitions share interconnect hardware, a reset may be provided to a first one of the at least two partitions while allowing the remaining of the at least two partitions to continue to operate. The interconnect hardware may provide means for reseting a first portion of the interconnect hardware associated with the first partition while allowing the remaining portions of the interconnect hardware to continue to operate undisturbed. The reset function may be triggered by hardware or software in either partition or by a system control facility.

Abstract: A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of time. The number of active data transfer interfaces is monitored, and a count value is incremented or decremented depending on the number of active data transfer interfaces. If the count value reaches a threshold value, it indicates that the number of data transfers for a predetermined period of time is exceptionally high, and therefore power consumption is high. Where the number of data transfers is high for a predetermined period of time, delays are injected into the handshake cycle to delay return of data acknowledge signals from data receivers to data transmitters. The delays are discontinued when the data transfer interface activity is reduced to a normal level.

Abstract: A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition.