Patents by Inventor Michael L. Korwin-Pawlowski

Michael L. Korwin-Pawlowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Planar P-N junction semiconductor structure with multilayer passivation
    Patent number: 5677562
    Abstract: A semiconductor device, which has a silicon body that includes at least one planar p-n junction that intersects a surface of the body, uses a multilayer arrangement that includes a first layer of thermally grown silicon dioxide, a second layer of Chemical-Vapor-Deposited (CVD) silicon nitride, a third layer of CVD oxygen-rich polysilicon, and a fourth layer of CVD silicon dioxide to passivate the junction. Common metallization contacts both the diffused region of the planar junction and the oxygen-rich polysilicon.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: October 14, 1997
    Assignee: General Instrument Corporation of Delaware
    Inventors: Michael L. Korwin-Pawlowski, Jean-Michel Guillot, James J. Brogle