Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.

Abstract: A workpiece, including a substrate and overlying layer, can be exposed to a region, such as a process chamber, to test for the presence of an analyte. Detected fluorescence emission signals during TXRD due to the substrate are significantly reduced, allowing the analyte to be detected at lower concentrations. In one embodiment, the substrate can principally include silicon, and the layer can include an organic layer (e.g., resist, polyimide, etc.) The organic layer allows analytes with an atomic number as low as 11 to be detected. Also, the detection limits for nearly all analytes can be reduced because the detector is not receiving a disproportionately larger number of fluorescence emission from silicon. In additional, areal information regarding the analyte with respect to position over the substrate can be obtained. Detection levels as low as 1E9 atoms/cm2 are possible.

Abstract: A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write address count, while a read address counter stores a read address count. Finally, a backup circuit receives a read address associated with data read from a slot of the plurality of slots. According to an alternate embodiment, a most significant bit circuit is coupled to an output of the write address counter for setting the most significant bit of the write address. A method of reading data stored in an asynchronous FIFO memory of an integrated circuit is also disclosed.

Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.

Abstract: A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.

Abstract: A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.

Abstract: A method and apparatus for test vector compression is described. More particularly, a response analyzer is described having a shift register and a multiple-input signature register. The shift register is used to perform a first vector space reduction, and the MISR is used to perform a second vector space compression. Accordingly the MISR may be scaled down in input width by a reduction factor of the shift register.

Abstract: A sense amplifier (10) is disclosed comprising: a connecting node (12) connectable to a plurality of logic cells (13) for reading the logic states thereof; at least one output (16, 18, 20); circuitry (14) for transferring the read logic states from the connecting node (12) to the at least one output; and a circuit (50) dynamically operative to limit the voltage at the connecting node (12) substantially to a predetermined voltage. In one embodiment, the circuit (50) includes a pass transistor (46) coupled between the connecting node (12) and the transferring circuit (14) and operative to conduct the logic states read from the logic cells to the transferring circuit; and a capacitive divider circuit (54, 56) coupled to a voltage source (Vdd) for producing at a node (52) thereof the predetermined voltage as a fraction of the voltage of the source, the node (52) being coupled to the pass transistor (46) to limit the voltage at the connecting node (12) substantially to the predetermined voltage.

Abstract: A person-specific monitor that provides sensor information regarding hazards to which the person is exposed and means to geolocate the person at the time of the exposure. The monitor also includes means to communicate with a remote base station. Information from the monitor can be downloaded at the base station for long term storage and analysis. The base station can also include means to recharge the monitor.

Abstract: A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like.