Abstract: A semiconductor packaging configuration is described in which a heat sink is bonded to a semiconductor chip or die and a conductor is bonded to the die and a metalized ceramic insulating body for achieving optimum heat transfer. Additionally, electrical matching and/or reduction of parasitic elements is achieved by a low pass matching filter comprising the capacitance of the chip or die, the capacitance of the metalized ceramic body and the inductance of the electrical conductor. This provides a significant improvement in power handling capabilities of a semiconductor chip or die operating at elevated temperatures and gigahertz frequencies. The electrical conductor geometry and its bonds provide a reduction of the thermal resistance of the package and also provides the inductance which forms part of the low pass matching filter.