Patents by Inventor Michael L. Spilo

Michael L. Spilo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6601091
    Abstract: A method for improving the performance and responsiveness of a computer program is presented. The system consists of a read-ahead mechanism that scans current data-sets and reads data-sets referenced within the current data-set prior to any actual request or access to the data set by the system. The determination of which data sets to access is made based upon a prioritization computed either through user defined settings or through heuristic observation of the system's behavior. The present invention has particular value in connection with Internet communications and access to remote data.
    Type: Grant
    Filed: March 28, 1996
    Date of Patent: July 29, 2003
    Assignee: Networks Associates Technology, Inc.
    Inventor: Michael L. Spilo
  • Patent number: 6460126
    Abstract: A system and method for managing scarce computer system memory resources has three aspects. A first aspect allows large data structures to be replaced by a pointer that causes an intentional fault to occur. The fault is trapped, and the invention interposes the required data. A second aspect associates data structures with both the task and the module that own the structure. The structure can be eliminated from memory when both the owning task and the owning module have terminated. A third aspect utilizes swapping techniques to maintain multiple local data areas for multiple tasks. In conjunction the three aspects of the invention provide improved resource availability and substantially unimpaired system performance.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: October 1, 2002
    Assignee: Networks Associates Technology, Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 6351794
    Abstract: A system and method for managing scarce computer system memory resources has three aspects. A first aspect allows large data structures to be replaced by a pointer that causes an intentional fault to occur. The fault is trapped, and the invention interposes the required data. A second aspect associates data structures with both the task and the module that own the structure. The structure can be eliminated from memory when both the owning task and the owning module have terminated. A third aspect utilizes swapping techniques to maintain multiple local data areas for multiple tasks.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: February 26, 2002
    Assignee: Network Associates, Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 6321293
    Abstract: A method for caching virtual memory paging requests and disk input/output requests utilizes a portion of the video memory as a location for paged memory as well as an alternative location for a disk cache system; the disk cache system is also capable of placing compressed data in a cache buffer. The portion of the video memory employed is off screen memory (OSM), access to which is controlled to make OSM available for paging or caching requirements. System operators may be monitored on a continuing basis to provide for a dynamic allocation of QSM.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: November 20, 2001
    Assignee: Networks Associates, Inc.
    Inventors: Daniel Fabrizio, Michael L. Spilo
  • Patent number: 6298422
    Abstract: The invention provides a method for reducing the memory requirements and CPU cycle consumption of an executing program in a suspended state suspends the program by intercepting the entry points of the program. The contents of the memory occupied by the program and its data objects are then discarded or compressed, wherein the compressed data is stored at another region in the memory. The memory region containing the uncompressed data is then designated as free memory.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: October 2, 2001
    Assignee: Network Associates, Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 6240531
    Abstract: A method for protecting a computer operating system from unexpected errors write-protects certain critical system components, thereby preventing corruption by application programs, and handles otherwise fatal program errors and infinite loops outside of the context of a malfunctioning program, permitting the program to be reactivated.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: May 29, 2001
    Assignee: Networks Associates Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 6208999
    Abstract: A file system for data file storage on a block storage device includes signature information embedded within each block allocated to a data file. Such signature information includes a file identification number, a sequence number within the file, and optional file type information. The signature information is used to reconstruct files on the block storage device in the event of damage to data files or critical system areas on the device. The directory structure for the file system is maintained as a self-contained flat database, stored as a B-tree for expedited searching, including full hierarchical pathnames for each directory entry, thereby enhancing the ability to recover files in a low level of the directory hierarchy when a middle level has been damaged.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: March 27, 2001
    Assignee: Network Associates, Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 6134601
    Abstract: A system and method for managing scarce computer system memory resources has three aspects. A first aspect allows large data structures to be replaced by a pointer that causes an intentional fault to occur. The fault is trapped, and the invention interposes the required data. A second aspect associates data structures with both the task and the module that own the structure. The structure can be eliminated from memory when both the owning task and the owning module have terminated. A third aspect utilizes swapping techniques to maintain multiple local data areas for multiple tasks.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: October 17, 2000
    Assignee: Networks Associates, Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 6064811
    Abstract: A method for improving the availability of global DOS memory under Microsoft Windows has two primary aspects. First, upper memory blocks are linked to the global heap to increase the amount of global DOS memory available. Second, a reserved area of global DOS memory is maintained to prevent generic memory requests from being fulfilled therefrom. Valid requests for global DOS memory are intercepted to ensure that they are able to be allocated out of global DOS memory or the reserved area. Taken in conjunction, the two aspects of the invention substantially decrease the probability that unavailability of global DOS memory will result in application or system failure.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: May 16, 2000
    Assignee: Network Associates, Inc.
    Inventors: Michael L Spilo, Jonathan A. Daub
  • Patent number: 5991856
    Abstract: A method for protecting a computer operating system from unexpected errors write-protects certain critical system components, thereby preventing corruption by application programs, and handles otherwise fatal program errors and infinite loops outside of the context of a malfunctioning program, permitting the program to be reactivated.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: November 23, 1999
    Assignee: Network Associates, Inc.
    Inventors: Michael L. Spilo, Jonathan A. Daub
  • Patent number: 5831987
    Abstract: A method for testing cache memory components of a computer system. The method tests RAM by detecting whether external memory caching can be disabled via software, and if not, the RAM is tested in segments large enough to ensure overflow of the primary L1 and secondary L2 CPU cache memory. The size of the L1 and L2 cache memories are measured by timing memory access speeds in Kb/Sec of successively larger blocks of memory. Additionally, a method for testing a particular region of system memory is provided, even if the memory region is in use by the operating system, which is accomplished by creating an isolated environment that switches the operating system off and on for each pass of the memory test.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: November 3, 1998
    Assignee: Network Associates, Inc.
    Inventor: Michael L. Spilo
  • Patent number: 5740367
    Abstract: A method and system for improving local area network throughput and thereby reducing traffic on the network hardware, allowing more workstations to be serviced by fewer servers. A further method for creating a bi-directional distributed processing system for cooperatively improving the local area network performance. In the preferred embodiment, a method is presented allowing workstations on a network to cache locally data normally retrieved from a network server or host machine.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: April 14, 1998
    Inventor: Michael L. Spilo
  • Patent number: 5559978
    Abstract: A method and system for increasing the efficiency of a virtual memory operating system is provided. In hardware assisted virtual memory, paging systems the preferred embodiment reduces the need for paging to or from non-memory devices by compressing and concatenating inactive regions in place. The compressed and concatenated regions are then queued for paging in the traditional virtual memory methodology. In this system, RAM memory made available by reducing the size of inactive regions is available immediately for use by the standard virtual memory paging system.
    Type: Grant
    Filed: January 18, 1995
    Date of Patent: September 24, 1996
    Assignee: Helix Software Company, Inc.
    Inventor: Michael L. Spilo
  • Patent number: 5543822
    Abstract: A method and system for increasing the throughput of video input and output operations in a computer system is provided. In a memory mapped video environment the preferred embodiment increases the speed of video access by redirecting the video I/O to system RAM and updating the actual memory mapped video asynchronously. Thus full CPU speed is attained in assembling the images, while the screen image is copied to video memory in the background and while the CPU is idle.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: August 6, 1996
    Assignee: Helix Software Company, Inc.
    Inventors: Michael L. Spilo, Jonathan Daub
  • Patent number: 5459869
    Abstract: A method and system for allowing protected mode device drivers and resident programs to load and execute from an MS/PC-DOS environment. A further method enabling such protected mode programs in an Intel x86 environment to transition between host environments is provided. In a preferred embodiment, a method for allowing for protected mode programs running in a DOS environment which can then transition and continue to function in a Windows environment. An improved method of mode switching for such drivers is also provided.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: October 17, 1995
    Inventor: Michael L. Spilo
  • Patent number: 5371871
    Abstract: A method for the allocation of RAM memory space in a microcomputer environment allows for one or more terminate and stay resident (TSR) or other programs to be stored on a remote memory device in a way that preserves their accessability. The method includes the installation of a supervisory program which traps calls for a displaced program and transfers a portion of another program, such as an application-type program, in RAM to remote memory while retrieving the called displaced program from remote memory into the RAM space previously occupied by the transferred portion. The swap function is performed in a manner which preserves the integrity of the swapped program, and which allows operation of the application program to be halted such that it may be restarted without loss upon return from remote memory. In another aspect of the invention a communication TSR is simulated to allow data transfers to the TSR to be processed even if the TSR is in remote memory.
    Type: Grant
    Filed: September 28, 1992
    Date of Patent: December 6, 1994
    Assignee: Helix Software Company, Inc.
    Inventor: Michael L. Spilo
  • Patent number: 5167030
    Abstract: A method for the allocation of RAM memory space in a microcomputer environment allows for one or more terminate and stay resident (TSR) or other programs to be stored on a remote memory device in a way that preserves their accessability. The method includes the installation of a supervisory program which traps calls for a displaced program and transfers a portion of another program, such as an application-type program, in RAM to remote memory while retrieving the called displaced program from remote memory into the RAM space previously occupied by the transferred portion. The swap function is performed in a manner which preserves the integrity of the swapped program, and which allows operation of the application program to be halted such that it may be restarted without loss upon return from remote memory. In another aspect of the invention a communication TSR is simulated to allow data transfers to the TSR to be processed even if the TSR is in remote memory.
    Type: Grant
    Filed: August 23, 1989
    Date of Patent: November 24, 1992
    Assignee: Helix Software Company, Inc.
    Inventor: Michael L. Spilo