Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.

Abstract: A unique trace word is assigned to each incoming signal routed by a sliced switch fabric having two or more parallel switches. The unique trace word is encoded into each incoming signal following an overall format that ensures that each sliced trace word (i.e., the subset of bits in the overall format routed by each parallel switch) also uniquely identifies each incoming signal. In this way, the present invention ensures that the switch configuration of each and every parallel switch can always be verified. As such, any improper switch configuration can be detected, including those misconfigurations in which all but one of the parallel switches are correctly configured as well as those misconfigurations in which all of the parallel switches are identically, but incorrectly configured.

Abstract: A high speed digital signal connection interface with reduced cross talk includes a multiple pin connector with disconnectable header and receptacle portions. The header is attached to a first set of signal carrying wire pairs communicating with a first signal processing unit. The receptacle is attached to a second set of signal carrying wire pairs communicating with a second signal processing unit. Within each of the first and second wire pair sets is a first wire pair subset carrying digital signals travelling in a first direction between the signal processing units, and a second wire pair subset carrying digital signals travelling in a second direction between the signal processing units. The first and second wire pair sets are attached to the corrector such that adjacent pin pairs of the connector carry only signals travelling in the same direction and such that connector pin pairs carrying signals travelling in opposite directions are not adjacent to each other.

Abstract: A test system for a evaluating a digital signal link includes a data signal generator, a data signal receiver, a digital signal link to be tested and a test interference signal injection (TISI) network connected as part of the digital signal link. The TISI network includes a data signal input port for receiving digital data signals generated by the data signal generator, a data signal output port for providing the digital data signals to the data signal receiver, and a controlled impedance data signal path carrying the digital data signals between the data signal input port and the data signal output port. An interference signal input port receives interference signals over a range of frequencies from an interference signal generator. One or more directional couplers directionally couple the interference signals into the data signal path toward either the data signal output port or the data signal input port at an impedance that substantially matches the impedance of the digital signal link.

Abstract: A system provides automatic protection switching in case of failure or degradation in a function. For example, a system node may have a working server function, a protection server function, one or more client functions, and a control function. In its baseline configuration, the working server function is active, meaning that it is operating on-line with respect to the client functions, while the protection server function is standby, meaning that it is either inactive (i.e., cold standby) or operating off-line with respect to the client functions (i.e., hot standby). The control function monitors the operations of the working server function, and, if a failure or degradation is detected, or if an externally generated switch command is received, the control function will (1) instruct the working server function to change its status from active to standby and (2) instruct the protection server function to change its status from standby to active.

Abstract: An Inverse Multiplexer is disclosed which first demultiplexes a first data rate input signal into a plurality of second lower data rate subsectional signals, where each subsectional signal is provided with a periodic synchronization marker and includes a data rate which is less than the channel data rate used to transmit that subsectional signal to a remote terminal. Programmable Multiplexers (PMUXs) then operate to each take one or more subsectional signals that are (1) clock synchronized to a PMUX clock, and (2) a rational fraction of the channel data rate, and map contiguously assigned time slots in a capacity domain frame for each subsectional signal to time slots of a time domain frame format using a 2-step or 3-step digit reverse technique. The resultant time domain format has the input subsectional capacity domain time slots substantially uniformly distributed over the time domain frame.

Abstract: Method and apparatus are disclosed for a programmable multiplexer for converting each of one or more input data signals, with individual data rates, into a second higher data rate signal by mapping contiguously arbitarily assigned Capacity Time Slots (CTSs) in a capacity domain frame to Time Slots in a Time Domain frame (TDTSs) so the TDTSs for each input signal are substantially uniformly spread throughout the TD frame. The programmable multiplexer receives separate input data rate signals which are clock synchronized to the multiplexer clock from separate synchronizers, and maps the capacity domain of the input signals to the time frame format using a 2-step or 3-step digit reverse technique. Both techniques decompose the capacity domain address into predetermined digits from predetermined number bases and then combine the digits to perform a similar computation using the number bases in reverse order.

Abstract: The present invention relates to a bootstrapping cross-polarization canceler which includes a noise-blanking limiter in the path before a correlation detector, and a processor which uses the output from the correlation detector to provide cross-polarization cancellation continuously or just during an outage condition where orthogonally received signals from a communication path include error rates which exceed a predetermined threshold. Alternatively, the processor can use the output of a pseudo error detection, which detects the error rate of the orthogonally received signals, when the error rates in the received signals are below the predetermined threshold in order to achieve convergence and cross-polarization cancellation in the canceler during a non-outage period.

Abstract: Eye violation detectors which provide either one of a "graded" or "half-graded" eye violation indicator technique. More particularly, the eye violation detector for practicing the "graded" technique provides an eye violation region in one or more eyes of a multiple eye pattern which is uniformly disposed on either side of the center of each of one or more eyes of the multiple pattern and includes a different amplitude in each of the eye patterns of interest. The eye violation detector for practicing the "half-graded" technique provides an eye violation region in one or more eyes of a multiple eye pattern which is disposed on only one side of the center of each of one or more eyes, except for the center eye of the multiple eye pattern, and includes a different amplitude in each of the eye patterns of interest.

Abstract: The present invention relates to an adaptive cross-polarization cancellation arrangement where a first desired polarized signal and a second interfering orthogonally polarized signal, including cross-polarization components, are concurrently received at an antenna. In the present arrangement, the orthogonally polarized components of the received signal are separated and transmitted along separate paths and recombined after the phase and amplitude of the separated polarized interfering signal sample has been appropriately adjusted for maximally cancelling cross-polarization components thereof in the other path.