Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: A method of reducing a number of bits required to transmit a digital signal using a PPP protocol is disclosed. The PPP protocol uses a predetermined byte for signalling. When that byte occurs, the following byte indicates signalling or alternatively, indicates a data byte having a value of the signalling byte. A value in the signalling byte is used to indicate a data byte, and other values are encoded to represent two or more signalling bytes within a predetermined spacing. Due to the look-ahead requirements, a time lag is introduced.

Abstract: A cache memory functioning as a circular buffer for use as a part historical, part predictive cache memory is provided. A first register contains data having a value corresponding to a cache memory location of a last instruction executed by a processor and a second register contains data having a value corresponding to a memory location in the cache memory of a last prefetched instruction. Prefetching of instructions from a main memory to the cache memory is disabled if the difference between the values in the first and second pointer registers exceeds a predetermined amount.