Patents by Inventor Michael L. Witkowski

Michael L. Witkowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7333485
    Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more of the ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which of the plurality of ports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: February 19, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael L. Witkowski, Dale J. Mayer, William J. Walker, Kirk D. Roller, Patricia E. Hareski, Gary B. Kotzur
  • Publication number: 20040068589
    Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more of the ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which of the plurality of ports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port.
    Type: Application
    Filed: September 22, 2003
    Publication date: April 8, 2004
    Inventors: Michael L. Witkowski, Dale J. Mayer, William J. Walker, Kirk D. Roller, Patricia E. Hareski, Gary B. Kotzur
  • Patent number: 6665733
    Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more of the ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which of the plurality of ports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port.
    Type: Grant
    Filed: September 23, 1997
    Date of Patent: December 16, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael L. Witkowski, Dale J. Mayer, William J. Walker, Kirk D. Roller, Patricia E. Hareski, Gary B. Kotzur
  • Patent number: 6430626
    Abstract: A network switch includes a plurality of first network ports coupled to a first bus, a plurality of second network ports coupled to a second bus, a bridge interface enabling data transfer between the buses, a switch manager controlling the flow of network data, and a processor for performing supervisory and control functions. The first and second network ports operate according to different network protocols, and the first and second buses operate according to different bus standards. During packet data transfers across the first bus, the bridge interface emulates a first network port. During packet data transfers across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports, thus relieving the processor of performing overhead functions associated with data transfers across the second bus.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: August 6, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Michael L. Witkowski, Gregory T. Chandler, Mohammad A. Khan, Gary B. Kotzur, Dale J. Mayer, William J. Walker
  • Patent number: 6389480
    Abstract: A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: May 14, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Gary B. Kotzur, Patricia E. Hareski, Michael L. Witkowski, Dale J. Mayer, William J. Walker
  • Patent number: 6260073
    Abstract: A network switch including one or more network ports for receiving and transmitting data is disclosed. The network switch also includes a processor, a switch manager, and memory. Each port includes a network interface, a data bus interface, and a processor port interface. A data bus is coupled to the data bus interface of each of the ports and the switch manager. A processor bus is coupled to a processor, the switch manager, and to the processor port interface of each of the ports. A memory bus is coupled to the memory and the switch manager. The switch manager periodically polls each of the network ports to determine the status of each port. The switch manager controls the flow of data between the network ports and memory based on the port status. The separate processor bus allows the processor to perform overhead functions, such as monitoring, determining status and configuration, without consuming valuable data bus bandwidth.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: July 10, 2001
    Assignee: Compaq Computer Corporation
    Inventors: William J. Walker, Gary B. Kotzur, Patricia E. Hareski, Dale J. Mayer, Michael L. Witkowski
  • Patent number: 6233242
    Abstract: A network switch including a central memory that stores device identification information, port numbers, control information, and packet data received at the ports of the switch. The memory includes a packet section that stores packet data and a device identification section that stores identification entries, where each entry corresponds to a network device coupled to a port of the switch. The switch includes a switch manager to control data flow between the ports and the central memory. Each of the identification entries includes a unique network address to identify one of the network devices and a port number to identify one of the network ports. Each of the identification entries is located within the central memory at a hash address derived by hashing the unique network address. Hash logic receives and hashes each network address to determine a hash address, which is used to access the identification entries. The memory is organized into a chain structure to enable quick access of entries.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: May 15, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Dale J. Mayer, Roger Richter, Michael L. Witkowski, Gary B. Kotzur, Patricia E. Hareski, William J. Walker
  • Patent number: 6233246
    Abstract: A network switch including a plurality of network ports for receiving and transmitting data, where each port includes at least one statistics register for storing statistics information, such as Ethernet statistical and configuration information. The switch also includes a switch manager, which further includes a memory, retrieval logic for detecting a statistics request signal and for respondingly retrieving the statistics information for storage in the memory, and response logic for asserting a statistics response signal after the statistics information is stored. A processor is coupled to the switch manager through a bus, where the processor asserts the statistics request signal and then detects assertion of the statistics response signal. Upon detecting the response signal, the processor retrieves the statistics information from the memory.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: May 15, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Patricia E. Hareski, William J. Walker, Gary B. Kotzur, Dale J. Mayer, Michael L. Witkowski
  • Patent number: 6222840
    Abstract: A system for performing concurrent read and write cycles in a network switch. The network switch includes several network ports, a data bus and a switch manager to execute a concurrent read and write cycle on the data bus by asserting a first port number to identify a source port followed by a second port number to identify a destination port. Each of the ports includes a network interface for sending and receiving data packets and a data interface to store the first port number, to assert data received from the network interface onto the data bus if that port is identified by the first port number, and to retrieve data from the data bus for transmission by the network interface if that port is identified by the second port number. In this manner, data is transferred directly between a source and a destination port without being buffered in the switch manager. The bandwidth of the data bus is increased since data is transferred only once on the data bus.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: April 24, 2001
    Assignee: Compaq Computer Corporation
    Inventors: William J. Walker, Gary B. Kotzur, Patricia E. Hareski, Michael L. Witkowski, Dale J. Mayer
  • Patent number: 6201789
    Abstract: A network switch including a plurality of network ports for communicating data packets, each port including logic for receiving a backpressure indication and for transmitting a jamming sequence to terminate transmission of a data packet being received. The switch includes a memory for temporarily storing data packets received by the ports, and a switch manager for determining one or more threshold conditions of the memory, for determining if a new data packet being received is to be stored in the memory for transmission by another port, and if so, for providing the backpressure indication to terminate the new data packet if a backpressure signal indicates that a threshold condition would be violated by storage of the new data packet. The jamming sequence is not sent if the packet is not intended to be stored in the switch, so that network devices coupled to a single port may continue to communicate to each other. The remaining ports of the switch are not effected.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: March 13, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Michael L. Witkowski, Gary B. Kotzur, Dale J. Mayer, William J. Walker, Patricia E. Hareski
  • Patent number: 6098110
    Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: August 1, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Michael L. Witkowski, Gregory T. Chandler, Mohammad A. Khan, Gary B. Kotzur, Dale J. Mayer, William J. Walker
  • Patent number: 6098109
    Abstract: A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: August 1, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Gary B. Kotzur, Patricia E. Hareski, Michael L. Witkowski, Dale J. Mayer, William J. Walker
  • Patent number: 6094434
    Abstract: A network switch including a separate cut-through buffer for facilitating cut-through mode of data transfer. The switch further includes a data bus coupled to each of the ports, a memory and a switch manager coupled to the data bus and to the memory for controlling data flow. The switch manager includes a receive buffer for handling data received by the switch, a transmit buffer for handling data to be transmitted by the switch, and a separate cut-through buffer for receiving data at any of the ports and for buffering the data to another one of the ports during cut-through mode of operation. The switch manager includes status memory, which includes programmable receive and transmit mode values for each of the ports, the modes selecting between cut-through and store-and-forward mode of operation for an indicated direction for each port.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: July 25, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Gary B. Kotzur, Dale J. Mayer, Michael L. Witkowski, William J. Walker, Patricia E. Hareski
  • Patent number: 5892926
    Abstract: A direct media independent interface (DMII) connection for a network device including a data link circuit, a connector, a clock circuit and a crossover connection. The data link circuit includes a reconciliation circuit that transmits and receives signals according to the MII standard. The clock circuit asserts at least one MII clock signal on the crossover connection to synchronize data transfer. The crossover connection crosses MII transmit signals with MII receive signals. A grounding circuit is optionally provided to ground one or more of the MII signals that are not required for the DMII connection. The connector may be a standard MII connector, or may be implemented as a minimum or reduced profile connector for carrying only the desired MII signals. The crossover connection is performed internally within the DMII port, or externally by a crossover cable. The cable is a standard MII cable, or is implemented as a minimum or reduced profile cable.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: April 6, 1999
    Assignee: Compaq Computer Corporation
    Inventors: Michael L. Witkowski, William J. Walker, Mohammad A. Khan, Gary B. Kotzur, Dale J. Mayer
  • Patent number: 5862338
    Abstract: A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: January 19, 1999
    Assignee: Compaq Computer Corporation
    Inventors: William J. Walker, Gary B. Kotzur, Michael L. Witkowski, Patricia E. Hareski, Dale J. Mayer