Abstract: A laminate tape that has a bottom layer of aggressive adhesive formulated to have sufficient adhesion to construction materials to as low as 20 degrees F. The adhesive is applied in a layer of about 2 to 5 mils. A second layer that is about 10 to 60 mils thick is made of rubberized asphalt, which provides self-sealing capabilities. In one embodiment, the first layer has strips of adhesive and sections of rubberized asphalt. The third layer is a film, which can be a thin, contiguous polymer, fabric or particulate. The laminate can be used where a strong adhesive is needed that will adhere to construction materials at or near 20 degrees Fahrenheit, while still retaining self-sealing characteristics.

Abstract: A laminate tape that has a bottom layer of aggressive adhesive formulated to have sufficient adhesion to construction materials to as low as 20 degrees F. The adhesive is applied in a layer of about 2 to 5 mils. A second layer that is about 10 to 60 mils thick is made of rubberized asphalt, which provides self-sealing capabilities. In one embodiment, the first layer has strips of adhesive and sections of rubberized asphalt. The third layer is a film, which can be a thin, contiguous polymer, fabric or particulate. The laminate can be used where a strong adhesive is needed that will adhere to construction materials at or near 20 degrees Fahrenheit, while still retaining self-sealing characteristics.

Abstract: A laminate tape that has a bottom layer of aggressive adhesive formulated to have sufficient adhesion to construction materials to as low as 20 degrees F. The adhesive is applied in a layer of about 2 to 5 mils. A second layer that is about 10 to 60 mils thick is made of rubberized asphalt, which provides self-sealing capabilities. In one embodiment, the first layer has strips of adhesive and sections of rubberized asphalt. The third layer is a film, which can be a thin, contiguous polymer, fabric or particulate. The laminate can be used where a strong adhesive is needed that will adhere to construction materials at or near 20 degrees Fahrenheit, while still retaining self-sealing characteristics.

Abstract: A laminate tape that has a bottom layer of aggressive adhesive formulated to have sufficient adhesion to construction materials to as low as 20 degrees F. The adhesive is applied in a layer of about 2 to 5 mils. A second layer that is about 10 to 60 mils thick is made of rubberized asphalt, which provides self-sealing capabilities. In one embodiment, the first layer has strips of adhesive and sections of rubberized asphalt. The third layer is a film, which can be a thin, contiguous polymer, fabric or particulate. The laminate can be used where a strong adhesive is needed that will adhere to construction materials at or near 20 degrees Fahrenheit, while still retaining self-sealing characteristics.

Abstract: A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.

Abstract: A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.

Abstract: The present invention comprises a scheduling assist function (scheduling assist) that enables a processor to schedule events and be notified when these events expire. In addition, the present invention includes features that enable a processor to associate these events with output channels and enable the processor to quickly locate output channels (links) that are available and ready to be serviced. The invention takes advantage of the fact that the scheduling assist can be dedicated exclusively to scanning tables in its own dedicated memories looking for events that have expired and/or output channels that are available and not involve the processor in the search for output channels that are available and ready to be serviced.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.

Abstract: A door boot for an appliance is positioned within the access opening of the appliance. A door is movable to a closed position cooperating with the door boot to seal the interior of the appliance cabinet. A relief groove is provided in the door boot which provides flexibility when the door is moved to its open position, and thereby reduces the force necessary to break the seal during opening of the door. The relief groove forms a flexible hinge.

Abstract: A door boot for an appliance is positioned within the access opening of the appliance. A door is movable to a closed position cooperating with the door boot to seal the interior of the appliance cabinet. A relief groove is provided in the door boot which provides flexibility when the door is moved to its open position, and thereby reduces the force necessary to break the seal during opening of the door. The relief groove forms a flexible hinge.

Abstract: A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces from the array to an external memory. The external memory stores non-transient data organized within data structures, such as forwarding and routing tables, for use in processing the transient data. Each processing element contains an instruction memory that allows programming of the array to process the transient data as processing element stages of baseline or extended pipelines operating in parallel.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: A technique is provided for use in testing replicated components (e.g., identical circuit components) of an electronic device for defects. In one aspect of this testing technique, the same test inputs may be broadcast, in parallel, from a single test interface to each of the replicated components of the electronic device under test. Respective test outputs generated by the replicated components in response to the test inputs may be supplied to a comparator, comprised in the electronic device, that compares the respective test outputs to each other and generates a fault signal if corresponding test outputs are not identical. This fault signal may be supplied to an external test interface pin of the single test interface, and its assertion may indicate that one or more of the replicated components may be defective. The respective test outputs may be multiplexed to permit output via an external interface of respective test outputs from a selected component.

Abstract: A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control system further includes an input header buffer (IHB) and an output header buffer (OHB), the latter comprising circuitry for receiving current transient data processed by the pipelines and for decoding control signals to determine a destination for the processed data. One destination is a feedback path that couples the OHB to the IHB and returns the processed data to the IHB for immediate loading into an available pipeline.

Abstract: A washing machine includes a washing machine cabinet having a top cover thereon. The top cover has an upwardly presented surface with an access opening therein and a first sloping surface extending downwardly and away from the access opening. A lid has a seal member thereon which engages the top cover for preventing fluid or condensation from moving away from the access opening down the first sloping surface of the top cover.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.

Abstract: A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory manager circuit. The context memories store transient “context” data for processing by the CPU in accordance with instructions stored in the instruction memory. The architecture further comprises data mover circuitry that cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine. An aspect of the architecture is the ability of the CPU to operate on the transient data substantially simultaneously with the passing of that data by the data mover.